(C). D-FF P:2 U3 D:4 U1 Q:5 U5 CLK:1 C:3. U2 100k P:2 U1 SN7474 Q:3 U4 0 L U5 1M CLK:1 U3 5 H CLK L H L H. L u 5.00u 7.50u 10.
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1 (register),. FFs, FF bit. n-bits n-ffs n-bits. FFs,. FFs. FFs. MSI. FFs. JK FFs. 2. -FF -FF FF. -FF,. :2 U5 1M K:1 U2 100k U4 0 U3 5 U1 SN7474 :3 1. -FF. T K u 5.00u 7.50u 10.00u reset lear 3 4. K:1 T K :2 U2 U3 :4 U1 :5 U5 :3 U FF reset () lear () reset = 0, = 1. ( ) lear = 0, = 0. ( ) reset lear 0. reset = 0, lear = 0, = u 5.00u 7.50u 10.00u
2 2 1, -FF. =1 = bit -Flip- Flop -FF.., A = A B B; A 1u A:2 B 1u B:4 A 2M 1M A:2 :1 A SN74100 A:3 B SN bit -FF. 2, Mz. B:4 K 1M A SN74100 A:3 B SN74100 B:5 T A 5. 2bit -Flip-Flop. T K A 5. A B B K: u 2.00u 3.00u 4.00u bit -Flip-Flop 2bit. 4 s A B... A B T A A B T A A u 2.00u 3.00u 4.00u 8. f A = 2Mz u 2.00u 3.00u 4.00u 9. f A = 1Mz B u 2.00u 3.00u 4.00u
3 3 10. f A = 0.5Mz 5. 4bit -Flip- Flop 11 4bit -FFs. FFs,. 4. FF,. FFs -. FFs (latch), (register). FFs FFs. (loading). bits,,. ATA 11.,, FF. (enable). =1. =0,.,. FFs..,,. AN FF. (load control). AN. FFs. FFs,.,.. Bus ( Insert) [0-3]. wire ATA Bus wire 0, 1, 2 3. Meters Bus isplay Voltage in Bus ( 12). Number System Binary ( 13), ATA ( 14). ATA : [0-3] 1M K:1 A0 SN74100 A1 SN74100 A2 SN74100 A3 SN :3 4:4 2:5 1:6
4 11. 4bit -Flip-Flop. T K J u 5.00u 7.50u 10.00u Bus isplay bit. 7. 4bit, Flip-Flops OA O -FF FF -,. FF. ( 17 18). 13. Binary. K T u 10.00u 15.00u 20.00u 14. binary bit JK Flip- Flop -Flip-Flop ATA : K:1 O OA 1 0 [0-3] K:1 OA:2 SW1 U9 U10 U bit, Flip-Flops OA O. U6 U6 U6 U5 U5 U5 U6 U5 U7 U7 U7 U7 U1 U2 U3 U4 8 8: : : :7 1 4 bit JK-Flip-Flop - Flip-Flop.. ( 15 16) T K OA J 1u J:2 U5 SN7404 J 3 U1 SN7476 U6 SN7404 J U2 SN7476 U7 SN J U3 SN7476 U8 SN J U4 SN [0-3] : K 1M K:1 K K bit JK FF -FF. K K u 5.00u 7.50u 10.00u 18. 4bit.
5 5 V : IBRARY ieee; US ieee.std_logic_1164.all; NTITY shiftreg IS GNRI (n: INTGR := 4); -- # of stages ORT (d, clk, rst: IN ST_OGI; q: OUT ST_OGI); N shiftreg; N barrel; ARITTUR RT OF barrel IS ROSS (inp, shift) IF (shift=0) TN outp <= inp; S outp(0) <= '0'; FOR i IN 1 TO inp'ig OO outp(i) <= inp(i-1); N OO; N IF; N ROSS; N RT; ARITTUR behavior OF shiftreg IS SIGNA internal: ST_OGI_VTOR (n-1 OWNTO 0); ROSS (clk, rst) IF (rst='1') TN internal <= (OTRS => '0'); SIF (clk'vnt AN clk='1') TN internal <= d &internal(internal'ft OWNTO 1); N IF; N ROSS; q <= internal(0); N behavior; barrel shifter. ( 8bit) 0 1. (shift=1), SB 0 ( ). shift=0, outp=inp, shift=1, outp(0)=0 outp(i)=inp(i-1) 1 i 7. IBRARY ieee; US ieee.std_logic_1164.all; NTITY barrel IS GNRI (n: INTGR := 8); ORT ( inp: IN ST_OGI_VTOR (n-1 OWNTO 0); shift: IN INTGR RANG 0 TO 1; outp: OUT ST_OGI_VTOR (n-1 OWNTO 0)); RAM IF IF (RAM). - (bus: data_in), - (bus: data_out), - (bus: addr), (clk) - (wr_ana), :
6 6 IF (wr_ena='1') TN IF (clk'vnt AN clk='1') TN memory(addr) <= data_in; N IF; N IF; N ROSS; data_out <= memory(addr); N ram; wr_ena 1, clk, o data_in addr. To data_out, addr., : wr_ena 0, q flip-flop d,. wr_ena 1, to, clk, d. RAM: IBRARY ieee; US ieee.std_logic_1164.all; NTITY ram IS GNRI ( bits: INTGR := 8; -- # of bits per word words: INTGR := 16); -- # of words in the memory ORT ( wr_ena, clk: IN ST_OGI; addr: IN INTGR RANG 0 TO words-1; data_in: IN ST_OGI_VTOR (bits-1 OWNTO 0); data_out: OUT ST_OGI_VTOR (bits-1 OWNTO 0)); N ram; ARITTUR ram OF ram IS TY vector_array IS ARRAY (0 TO words-1) OF ST_OGI_VTOR (bits-1 OWNTO 0); SIGNA memory: vector_array; ROSS (clk, wr_ena) VARIAB SIGNA : VARIAB SIGNA. (dout) (din) 4. VARIAB (a, b, c). (, c, b, a). flip-flops ROSS Solution 1: NTITY shift IS ORT ( din, clk: IN BIT; dout: OUT BIT); N shift; ARITTUR shift OF shift IS ROSS (clk) VARIAB a, b, c: BIT; IF (clk'vnt AN clk='1') TN dout <= c; c := b; b := a; a := din; N IF; N ROSS; N shift;, SIGNA. (clk),,, Solution 2: NTITY shift IS
7 7 ORT ( din, clk: IN BIT; dout: OUT BIT); N shift; ARITTUR shift OF shift IS SIGNA a, b, c: BIT; ROSS (clk) IF (clk'vnt AN clk='1') TN a <= din; b <= a; c <= b; dout <= c; N IF; N ROSS; N shift;,., ( ), c := din. c (dout <= c) clk., Solution 3: NTITY shift IS ORT ( din, clk: IN BIT; dout: OUT BIT); N shift; ARITTUR shift OF shift IS ROSS (clk) VARIAB a, b, c: BIT; IF (clk'vnt AN clk='1') TN a := din; b := a; c := b; dout <= c; N IF; N ROSS; N shift; reset : bit (q) 4 o (d). To reset flipflops 0., SIGNA flip-flops, VARIAB. ( 4 flipflops). 1,. -- Solution 1: -- With an internal SIGNA IBRARY ieee; US ieee.std_logic_1164.all; NTITY shiftreg IS ORT ( d, clk, rst: IN ST_OGI; q: OUT ST_OGI); N shiftreg; ARITTUR behavior OF shiftreg IS SIGNA internal: ST_OGI_VTOR (3 OWNTO 0); ROSS (clk, rst) IF (rst='1') TN internal <= (OTRS => '0'); SIF (clk'vnt AN clk='1') TN internal <= d & internal(3 OWNTO 1); N IF; N ROSS; q <= internal(0); N behavior; 2,, ( ). -- Solution 2: -- With an internal VARIAB IBRARY ieee; US ieee.std_logic_1164.all; NTITY shiftreg IS ORT ( d, clk, rst: IN ST_OGI;
8 8 q: OUT ST_OGI); N shiftreg; ARITTUR behavior OF shiftreg IS ROSS (clk, rst) VARIAB internal: ST_OGI_VTOR (3 OWNTO 0); IF (rst='1') TN internal := (OTRS => '0'); SIF (clk'vnt AN clk='1') TN internal := d & internal(3 OWNTO 1); N IF; q <= internal(0); N ROSS; N behavior; 4bit : -- size of the register ORT ( lock, lear, oad: IN ST_OGI; : IN ST_OGI_VTOR(size OWNTO 0); : OUT ST_OGI_VTOR(size OWNTO 0)); N reg; ARITTUR Behavior OF reg IS ROSS(lock, lear) IF lear = '1' TN <= (OTRS => '0'); SIF (lock'vnt AN lock = '1') TN IF oad = '1' TN <= ; N IF; N IF; N ROSS; N Behavior; 4bit - -, : : lear oad 1 X ( ) , : V : IBRARY I; US I.ST_OGI_1164.A; NTITY reg IS GNRI (size: INTGR := 3); : : Shift 0 1 bit Serial_in : -- flip-flop with enable IBRARY I; US I.ST_OGI_1164.A; NTITY _flipflop IS ORT(, lock, : IN ST_OGI;
9 9 : OUT ST_OGI); N _flipflop; ARITTUR Behavior OF _flipflop IS ROSS(lock) IF (lock'vnt AN lock = '1') TN IF ( = '1') TN <= ; N IF; N IF; N ROSS; N Behavior; -- 4-bit shift register IBRARY I; US I.ST_OGI_1164.A; : SSel1 SSel0 0 0 ( ) : NTITY ShiftReg IS ORT(Serial_in, lock, Shift : IN ST_OGI; : OUT ST_OGI_VTOR(3 downto 0)); N ShiftReg; ARITTUR Structural OF ShiftReg IS SIGNA N0, N1, N2, N3 : ST_OGI; OMONNT _flipflop ORT (, lock, : IN ST_OGI; : OUT ST_OGI); N OMONNT; U1: _flipflop ORT MA (Serial_in, lock, Shift, N3); U2: _flipflop ORT MA (N3, lock, Shift, N2); U3: _flipflop ORT MA (N2, lock, Shift, N1); U4: _flipflop ORT MA (N1, lock, Shift, N0); (3) <= N3; (2) <= N2; (1) <= N1; (0) <= N0; N Structural; : V : IBRARY I; US I.ST_OGI_1164.A; NTITY shiftreg IS ORT ( lock: IN ST_OGI; SSel: IN ST_OGI_VTOR(1 OWNTO 0); Serial_in: IN ST_OGI; : IN ST_OGI_VTOR(3 OWNTO 0); Serial_out: OUT ST_OGI; : OUT ST_OGI_VTOR(3 OWNTO 0)); N shiftreg; ARITTUR Behavioral OF shiftreg IS SIGNA content: ST_OGI_VTOR(3 OWNTO 0); ROSS(lock) IF (lock'vnt AN lock='1') TN AS SSel IS WN "01" => -- load content <= ; WN "10" => -- shift right, pad with bit from Serial_in content <= Serial_in & content(3
10 OWNTO 1); WN OTRS => NU; N AS; N IF; N ROSS; <= content; Serial_out <= content(0); N Behavioral; 10
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