Xilinx V H D L. Design with VHDL(1) Agenda. Basic Rule for VHDL Coding. Simple Gate Logic (1) Simple Gate Logic (2) Basic Rule for VHDL Coding

Transcription

1 gen Xilinx V H L esign with VHL ( Comintionl Logi ) L 1 esign with VHL ( Sequentil Logi ) Presente L 2 esign with VHL ( Hierh esign, esign Flow ) si Rule for VHL Coing si Rule for VHL Coing esign with VHL(1) (Comintionl Logi) ; (Line ), Spe ( Line Chnge, Tp ) Reserve Wor User efine Nme Sntx Pttern Comment -- Line Comment Line Line -- Tpe Simple Gte Logi (1) Simple Gte Logi (2) VHL Coe for Simple Gte (1) VHL Coe for Simple Gte (2) entit n2 is : in st_logi; : in st_logi; : out st_logi en n2; rhiteture _n of n2 is Gte entit gte is, : in st_logi;, : in st_logi; : out st_logi en gte; rhiteture _g of gte is Gte <= n ; <= n or n ; en _n; en _g; -- Logi Opertor : N OR NOT NOR NN XOR -- Coe Logi igrm?

2 Simple Gte Logi (3) Simple Gte Logi (4) VHL Coe for Simple Gte (3) Signl efine entit gte is,,, : in st_logi; : out st_logi en gte; rhiteture _g of gte is <= ( n ) or ( n not en _g; -- Not Logi Opertor -- Gte entit gte is,,, : in st_logi; : out st_logi en gte; rhiteture _g of gte is signl e,f : st_logi; e <= n ; f <= n ; <= e or f; en _g; -- Signl Entit Noe Gte eoer Logi (1) eoer Logi (2) eoer with Gte Comintion Truth Tle eoer Coe C Y eoer eoer with Gte Comintion entit e is,,, : in st_logi; : out st_logi en e; rhiteture _e of e is signl v3,v4,v6,v : st_logi; v3 <= (not ) n (not ) n n ; v4 <= (not ) n n (not ) n (not v6 <= (not ) n n n (not v <= n (not ) n n (not <= v3 or v4 or v6 or v; en _e; eo eoer Logi (3) eoer Logi (4) eoer with ehviorl Coe(1) entit e is,,, : in st_logi; : out st_logi en e; rhiteture _e of e is signl in : st_logi_vetor(3 ownto 0 signl v3,v4,v6,v : st_logi; in <= & & & ; v3 <= 1 when in = 0011 else 0 ; v4 <= 1 when in = 0100 else 0 ; v6 <= 1 when in = 0110 else 0 ; v <= 1 when in = 1010 else 0 ; <= v3 or v4 or v6 or v; en _e; eo eoer with ehviorl Coe(2) entit e is,,, : in st_logi; : out st_logi en e; rhiteture _e of e is signl in : st_logi_vetor(3 ownto 0 -- signl v3,v4,v6,v : st_logi; in <= & & & ; <= 1 when in = 0011 else 1 when in = 0100 else 1 when in = 0110 else 1 when in = 1010 else 0 ; en _e; eo

3 eoer Logi (5) Multiplexer Logi (1) eoer with ehviorl Coe(3) entit e is,,, : in st_logi; : out st_logi en e; rhiteture _e of e is signl in : st_logi_vetor(3 ownto 0 eo 2 to 1 Multiplexer 2 to 1 mux Gte Coe sel 2 to 1 mux ehviorl Coe I0 I1 Mux in <= & & & ; <= 1 when (in = 0011 ) or (in = 0100 ) or (in = 0110 ) or (in = 1010 ) else 0 ; en _e; Multiplexer Logi (2) Multiplexer Logi (3) 2 to 1 Multiplexer (Gte Comintion) 2 to 1 Multiplexer (ehviorl) entit mux2 is i0,i1 : in st_logi; sel : in st_logi; : out st_logi en mux2; rhiteture gte_mux2 of mux2 is sel I0 I1 Mux entit mux2 is i0,i1 : in st_logi; sel : in st_logi; : out st_logi en mux2; rhiteture ehve_mux2 of mux2 is sel I0 I1 Mux <= (i0 n not sel) or (i1 n sel <= i0 when sel = 0 else i1; en gte_mux2; en ehve_mux2; Multiplexer Logi (4) Multiplexer Logi (5) 4 to 1 Multiplexer (1) 4 to 1 Multiplexer (2) entit mux4 is i0,i1,i2,i3 : in st_logi; sel : in st_logi_vetor(1 ownto 0 : out st_logi en mux4; sel I0 I1 rhiteture ehve_mux4 of mux4 is <= en ehve_mux4; i0 when sel = 00 else i1 when sel = 01 else i2 when sel = 10 else i3 when sel = 11 else 0 ; 2 Mux I2 I3 entit mux4 is i0,i1,i2,i3 : in st_logi; sel : in st_logi_vetor(1 ownto 0 : out st_logi en mux4; sel I0 I1 rhiteture ehve_mux4 of mux4 is with sel selet <= i0 when 00, i1 when 01, 2 i2 when 10, i3 when 11, 0 when others; en ehve_mux4; Mux I2 I3

4 Multiplxer Logi(6) Comprtor Logi (1) - 4 to 1 Multiplexer Comprtor Smol Coe I3 I2 I1 I0 Z I0 I1 I2 I3 Sel Y Output = E, G, L Input = [3:0], [3:0] E G L = > < Comp E G L <when else> <with selet when> VHL Reltionl Opertor : =, /=, <, <=, >, >= Comprtor Comprtor Logi (2) entit omp is, : in st_logi_vetor(3 ownto 0 eq,g,l : out st_logi en omp; rhiteture _omp of omp is eq <= 1 when = else 0 ; g <= 1 when > else 0 ; l <= 1 when < else 0 ; en _omp; Comp E G L Constnt Comprtor Comprtor Logi (3) Single Input Constnt 0100 Comprtor 0100 Comp E G L? Comp with 0100 E G L rithmeti Opertor (1) rithmeti Opertor (2) rithmeti Opertor (1) rithmeti Opertor (2) use ieeest_logi_unsignell; entit er is, : in st_logi_vetor(3 ownto 0 : out st_logi_vetor(3 ownto 0) en er; rhiteture _er of er is <= + ; en _er; -- rithemti Opertors : +, -, *, /, ** er Y -- Coe rhiteture use ieeest_logi_unsignell; entit er is,,, : in st_logi_vetor(3 ownto 0 : out st_logi_vetor(3 ownto 0) er en er; rhiteture _er of er is <= ; C en _er; Y

5 rithmeti Opertor (3) rithmeti Opertor (4) rithmeti Opertor (3) rithmeti Opertor (4) -- Coe rhiteture -- Overflow use ieeest_logi_unsignell; use ieeest_logi_unsignell; entit er is,,, : in st_logi_vetor(3 ownto 0 : out st_logi_vetor(3 ownto 0) en er; rhiteture _er of er is <= ( + ) + ( + C en _er; er Y entit er is, : in st_logi_vetor(3 ownto 0 : out st_logi_vetor(4 ownto 0) en er; rhiteture _er of er is <= ( 0 & ) + ( 0 & en _er; er Y Comintionl Logi Summr Snthesis Logi Opertor rithmeti Opertor Reltionl Opertor Contention us < it iretion > when < > else with < > selet < > when RTL Snthesis : Single Cle Hr Wre rhiteture esign Mnul ( + + C + ) vs ( + ) + (C + ) Snthesis Tool Snthesis Tool? FF rhiteture esign with VHL(2) (Sequentil Logi ) - Sequentil Logi Proess - if then else -lok entit FF is, : in st_logi; : in st_logi; : out st_logi en entit FF ; rhiteture ehve of FF is proess (, ) if = 1 then <= 0 ; elsif ( event n = 1 ) then <= ; en ehve;

6 Proess * Sequentil Control * rhiteture * Sensitivit List Signl * Proess Instrution (Proess Conurrent ) proess (sensitivit list here) If then else * lterntive Seletion * Proess * Seletion Cover if (onition 1) then elsif (onition 2) then elsif (onition 3) then else en if; Clok efine * Clok * Proess if then else * Rising, Flling Ege * Proess Clok, Ege (signl event n signl = 1 ) -- rising ege (signl event n signl = 0 ) -- flling ege - si Register Register entit reg is : in st_logi_vetor(7 ownto 0 rst : in st_logi; lk : in st_logi; q : out st_logi_vetor(7 ownto 0) en reg; rhiteture ehve of reg is proess (lk,rst) q <= (others => 0 ) ; elsif ( lk event n lk = 1 ) then q <= ; en ehve; Reg - si Counter Counter (1) I/O Port iretion Tpes -Entit Port iretion Cnt + 1 Reg * IN : Input Onl ( in ) * OUT : Output Onl (Cn not fee-k) ( out) Cnt * INOUT : In n Out ( inout) * UFFER : Output Onl (Cn Fee-k) ( uffer)

7 Counter (1) Counter (2) - si Counter - Counter with Enle Logi use ieeest_logi_unsignell; entit nt is rst : in st_logi; lk : in st_logi; q : out st_logi_vetor(7 ownto 0) en nt ; rhiteture ehve of nt is signl tq : st_logi_vetor(7 ownto 0 proess (lk,rst) tq <= (others => 0 ) ; elsif ( lk event n lk = 1 ) then tq <= tq + 1; q <= tq; en ehve; Cnt EN CntE + 1 CntE 0 1 EN Reg - Counter with Enle Counter (3) use ieeest_logi_unsignell; entit nte is rst,en : in st_logi; lk : in st_logi; q : out st_logi_vetor(7 ownto 0) en nte ; rhiteture ehve of nte is signl tq : st_logi_vetor(7 ownto 0 proess (lk,rst) tq <= (others => 0 ) ; elsif ( lk event n lk = 1 ) then if en = 1 then tq <= tq + 1; q <= tq; en ehve; EN CntE Counter (4) - Counter with Enle n Snhronous Reset Logi * Enle Snhronous Reset? + 1 CntESR 0 1 EN 0 1 SR Reg Counter (5) - Counter with Enle n Sn Reset If / Else Sttements use ieeest_logi_unsignell; entit ntsre is rst,en : in st_logi; lk,sr : in st_logi; q : out st_logi_vetor(7 ownto 0) en ntsre ; rhiteture ehve of ntsre is signl tq : st_logi_vetor(7 ownto 0 proess (lk,rst) tq <= (others => 0 ) ; elsif ( lk event n lk = 1 ) then if sr = 1 then tq <= (others => 0 ) ; elsif en = 1 then tq <= tq + 1; q <= tq; en ehve; SR EN ntsre proess if ( oolen expression ) then sequentil sttements; proess if ( oolen expression ) then else The if / else sttement llows opertions to e performe se on ertin onitions It hs three si forms proess if ( oolen expression ) then elsif ( oolen expression ) then elsif ( oolen expression ) then

8 If/Elsif Exmple n Rules Cse Sttement C Sel Z 1 The first onition foun to e true will e exeute 2 Conitions n overlp 3 The first onition of n if / elsif will hve priorit proess (,, C,, Sel ) If (Sel= 00 ) then Z <= ; C elsif (Sel= 01 ) then Z <= ; elsif (Sel= 10 ) then Z <= C; else Z <= ; Z en if; en proess ; Compre with Sme Funtion Coe Z <= when (Sel = 00 ) else when (Sel = 01 ) else C when (Sel = 10 ) else ; proess ( ) se ( seletor expression ) is when => when => when => en se ; The CSE sttement llows opertions to e performe se on the vlue of single expression, s inite the seletor expression proess () se ( seletor expression ) is when => when others => en se ; C Sel Z Cse Exmples n Rules Cse sttements re preferle for LUT rhitetures given tht most snthesis tools will proue mux, or similrl miniml logi level struture 1 ll possile onitions must e speifie 2 No onitions n overlp 3 ll rnge speifitions must e of isrete tpe proess (,, C,, Sel ) se Sel is when 00 => Z <= ; when 01 => Z <= ; when 10 => Z <= C ; when others => Z <= ; en se ; Compre with Sme Funtion Coe With sel selet Z <= when 00, when 01, C when 10, when others; Loop Sttements Loop sttements n e onstrute for n repetitive opertion There re ifferent forms, eh hving ifferent metho of ontrol We shll exmine the for loop proess (, _us ) for I in 0 to 7 loop C_us (I) <= n _us (I) ; en loop ; The loop vrile Inex is not elre, n is not visile outsie the loop It is trete s onstnt With eh loop itertion, it suessivel ssumes the isrete vlues inite in the rnge S to P Shift Register - For Loop Seril in Prllel Out Shift Register SIN StoP - Seril in Prllel Out Shift Register S to P Shift Register entit s2p is rst,sin : in st_logi; lk : in st_logi; q : out st_logi_vetor(7 ownto 0) en s2p; rhiteture ehve of s2p is signl tq : st_logi_vetor(7 ownto 0) proess (lk,rst) tq <= (others => 0 ) ; elsif (lk event n lk = 1 ) then tq(0) <= sin; for I in 1 to 7 loop tq(i) <= tq(i-1 en loop; en if; q <= tq; en ehve; SIN StoP

9 uiz 1 Proess? 2 If Cse? 3 Entit Clok? esign with VHL (3) Hierrh esign esign Flow 4 Proess? CLK RST Hierrhil esign (1) Inrementl Counter 1 Coing Lirr ieee; use ieeest_logi_unsignell; entit 1 is : in st_logi_vetor(7 ownto 0 : out st_logi_vetor(7 ownto 0) en 1; rhiteture _ of 1 is <= + 1; en _; CNT Coing entit nt is rst,lk in st_logi; q : out st_logi_vetor(7 ownto 0) en 1; rhiteture _nt of nt is omponent 1 in st_logi_vetor(7 ownto 0 : out st_logi_vetor(7 ownto 0) en omponent; signl tq,in : st_logi_vetor(7 ownto 0 u0 : 1 port mp ( => tq, => in proess (rst,lk) tq <= (others => 0 elsif lk event n lk = 1 then tq <= in; en if; q <= tq; en _nt; Component elrtion U0 : 1 port mp ( tq, in 1Sstem efine 2 lgorithm efine 3 rhiteture efine 4 VHL Coe esign 5 Funtion Simultion 6 S n t h e s i s 7 Timing Simultion 1 Ple & Route 9 Timing Simultion 2 10 Trget evie 11 Hr Wre Test 12 Mss Proution esign Flow esign Flow (1) 1 Sstem efine - Sstem 2 lgorithm efine -Sstem lgorithm 3 rhiteture esign - lgorithm H/W rhiteture - Timing Chrt 4 Ciruit esign (VHL Coing) 5 Funtion Simultion -Stimulus Test enh (Simultor ) - lgorithm Timing Chrt

10 1Sstem efine 2 lgorithm efine 3 rhiteture efine 4 VHL Coe esign 5 Funtion Simultion 6 S n t h e s i s 7 Timing Simultion 1 Ple & Route 9 Timing Simultion 2 10 Trget evie 11 Hr Wre Test 12 Mss Proution esign Flow esign Flow (2) 6 Snthesis - Trget Tehnolog Lirr, Constrint 7 Timing Simultion 1 -Snthesis Cell el Simultion Ple & Route - Trget evie (Timing, Size) Cell, 9 Timing Simultion 2 - Cell + Routing el Simultion 10 Trget evie - SIC : Gte rr, Stnr Cell, Full Custom (Test Vetor,NRE) - PL : FPG, PL (Progrmming) 11 Hr Wre Test (On or, Test Logi) 12 Mss Proution 90% vs Erl etet Error => Chep to fix eug & Enhnement Solution 1 esign - Timing Mrgin, Fn Out - Snhronous esign (Counter, Exmple) - Trget Tehnolog (FPG Exmple) 2 Snthesis Control(Tool Performne, Option) 3 Ple n Routing Control Xilinx VHL Summr Xilinx VHL EN