Chapter 7. Registers & Register Transfers. J.J. Shann. J. J. Shann

Transcription

1 Chapter 7 Registers & Register Transfers J. J. Shann J.J. Shann

2 Chapter Overview 7-1 Registers and Load Enable 7-2 Register Transfers 7-3 Register Transfer Operations 7-4 A Note for VHDL and Verilog Users Only 7-5 Microoperations 7-6 Microoperatrions on a Single Register 7-7 Register Cell Design 7-8 Multiplexer and Bus-Based Transfer for Multiple Registers 7-9 Serial Transfer and Microoperations 7-1 HDL Representation for Shift Registes and Counters VHDL 7-11 HDL Representation for Shift Registes and Counters Verilog 7-12 Chapter Summary J.J. Shann 7-2

3 Part I: Registers and Counters 7-1 Registers and Load Enable 7-6 Microoperatrions on a Single Register (Shift registers, Ripple counter, Synchronous binary counters, other counters) Part II: Register Transfers 7-2 Register Transfers 7-3 Register Transfer Operations 7-5 Microoperations 7-7 Register Cell Design 7-6 Microoperatrions on a Single Register (Multiplexer-Based Transfers) 7-8 Multiplexer and Bus-Based Transfer for Multiple Registers 7-9 Serial Transfer and Microoperations 7-12 Chapter Summary J.J. Shann 7-3

4 Part I Registers and Counters J.J. Shann

5 Clocked seq ckt: sync seq ckt consists of a group of flip-flops and combinational gates connected to form a feedback path. Flip-flops + Combinational gates (essential) (optional) Register: consists of a group of flip-flops capable of storing binary information and gates that determine how the information is transferred into the register. Counter: is essentially a register that goes through a predetermined sequence of states. J.J. Shann 7-5

6 Lecture Contents A. Simplest register ( 7-1) B. Register with parallel load ( 7-1) C. Shift registers ( 7-6) D. Ripple counter ( 7-6) E. Synchronous binary counters ( 7-6) F. Other counters ( 7-6) J.J. Shann 7-6

7 A. Simplest Register ( 7-1) Simplest register: consists of only flip-flops w/o any gates. E.g.: a 4-bit register with asynchronous clear input J.J. Shann 7-7

8 B. Register w/ Parallel Load ( 7-1) Load Approach 1: Load control input through the C inputs of the f-fs clock gating Approach 2: Load control input through the D inputs of the f-fs J.J. Shann 7-8

9 Approach 1: Load control input through the C inputs of the f-fs clock gating prevent the clock from reaching the clock input to the ckt if the contents of the reg are to be left unchanged C inputs = Load + Clock * Inserting gates in the clock pulse path produces different propagation delays b/t clock and the inputs of f-fs w/ and w/o clock gating. clock skew J.J. Shann 7-9

10 Approach 2: Load control input through the D inputs of the f-fs D i = Load I i + Load i (Load) E.g.: 4-bit register w/ parallel load J.J. Shann 7-1

11 C. Shift Registers ( 7-6) Shift register: a register capable of shifting its binary information in one or both direction Simplest shift register: unidirectional J.J. Shann 7-11

12 Shift Register w/ Parallel Load Shift register w/ parallel load: Functional table: D i = Shift Load i + Shift Load Ii + Shift i 1 Clock J.J. Shann 7-12

13 E.g.: 4-bit shift register w/ parallel load J.J. Shann 7-13

14 Bidirectional Shift Register Bidirectional shift register direction = shl = 1 shr direction SI of shr SO of shl i + 1 Flip-Flops i i 1 SO of shr SI of shl CLK D i = direction A i+1 + direction A i 1 J.J. Shann 7-14

15 Bidirectional Shift Reg w/ Parallel Load Bidirectional shift register w/ parallel load: Mode control Register S 1 S operation No change 1 Shift down 1 Shift up 1 1 Parallel load D i = S 1 S i + S 1 S i-1 + S 1 S i+1 + S 1 S I i J.J. Shann 7-15

16 D. Ripple Counters ( 7-6) Counter: a register that goes through a prescribed sequence of states upon the application of input pulses: Input pulses: may be clock pulses or originate from some external source Timing: may occur at regular or irregular intervals of time The sequence of states: may follow the binary number sequence ( Binary counter) or any other sequence of states J.J. Shann 7-16

17 Categories of counters: 1. Ripple counters: (D) The flip-flop output transition serves as a source for triggering other flip-flops. The C input of some or all flip-flops are triggered not by the common clock pulses. (not synchronous) 2. Synchronous counters: (E) The C inputs of all flip-flops receive the common clock. * T or JK flip-flops J.J. Shann 7-17

18 Binary Ripple Counter Binary count-up counter: E.g.: 4-bit binary count-up ripple counter J.J. Shann 7-18

19 Observations: FF :C = Clock pulse D = FF 1 :C 1 = ( ) ( ) D 1 = 1 FF 2 :C 2 = 1 ( ) 1 ( ) D 2 = 2 FF 3 :C 3 = 2 ( ) 2 ( ) D 3 = J.J. Shann 7-19

20 1 2 3 J.J. Shann 7-2

21 * Problem of ripple counter: Accumulation of propagation delay E.g.: 2-bit binary count-up ripple counter 1 CP J.J. Shann 7-21

22 Binary count-down counter: E.g.: 4-bit binary count-down ripple counter Downward Counting Sequence * Modify the figure in p.7-19: Connect the true output of each f-f to the C input of the next f-f. J.J. Shann 7-22

23 Summary: are asynchronous ckts Adv.: simple hardware Disadv.: become ckt w/ delay dependence and unreliable op large ripple counters can be slow ckts the length of time required for the ripple to finish J.J. Shann 7-23

24 E. Synchronous Counters ( 7-6) Sync counter: A common clock triggers all flip-flops simultaneously. Symbol: Design procedure: We can apply the same procedure of sync seq ckts. Sync counter is simpler than general sync seq ckts. No need to go through a sync seq logic design process. J.J. Shann 7-24

25 Example E.g.: 4-bit sync count-up binary counter w/ count enable line Approach 1: design procedure of sync seq ckt (Ch6) Present state Nest state EN = EN = Output CO 1 D EN = + EN = EN D1 = 1 ( EN) D2 = 2 ( 1 EN) D3 = 3 ( 2 1 EN) CO = CO: is used to extend the counter to more stages J.J. Shann 7-25

26 J.J. Shann 7-26 Approach 2: observation ) ( 1 1 EN D = ) ( EN D = ) ( EN D = CO = EN EN D = + = EN

27 Approach 3: an incrementer (Ch5) + D f-fs D 3 D 2 D 1 D = EN D = EN D1 = 1 ( EN ) D2 = 2 ( 1 EN) D3 = 3 ( 2 1 EN) CO = J.J. Shann 7-27

28 Alternative Designs for Binary Counters Two alternative designs for binary counters: Serial counter: serial gating Parallel counter: parallel gating * analogous to the ripple carry adder C 1 C 2 * analogous to the carry lookahead adder C 3 J.J. Shann 7-28

29 Binary Counter by Using JK Flip-Flops E.g.: 4-bit count-up binary counter w/ JK f-fs Binary count sequence: 3-bit A 2 A 1 A J.J. Shann 7-29

30 A 2 A 1 A J = K = EN J 1 = K 1 = EN A J 2 = K 2 = EN A 1 A J 3 = K 3 = EN A 2 A 1 A J.J. Shann 7-3

31 Up-Down Binary Counter Up-down binary counter: E.g.: 4-bit up-down binary counter J.J. Shann 7-31

32 J.J. Shann 7-32 EN D = ) ) (( 1 1 EN S S D + = ) ) (( EN S S D + = ) ) (( EN S S D + = S = up-counting 1 down-counting Up-down counter:

33 Binary Counter w/ Parallel Load E.g.: 4-bit count-up binary counter w/ parallel load Function table: Load Count I 3 I 2 I 1 I D i = Load Count i + Load Count ( i i-1 ) + Load I i J.J. Shann 7-33

34 E.g.: 4-bit count-up binary counter w/ parallel load 1 J.J. Shann 7-34

35 E.g.: 4-bit count-up binary counter w/ parallel load 1 1 D ( ) J.J. Shann 7-35

36 Generating Other Count Sequences Generate any count sequence: E.g.: design a BCD counter by using a counter w/ parallel load & async clear J.J. Shann 7-36

37 J.J. Shann 7-37

38 F. Other Counters ( 7-6) Counters: can be designed to generate any desired sequence of states Binary counter (D, E) BCD counter Divide-by-N counter: modulo-n counter a counter that goes through a repeated sequence of N states The sequence may follow the binary count or may be any other arbitrary sequence. J.J. Shann 7-38

39 BCD Counter State diagram & Count sequence: J.J. Shann 7-39

40 Synchronous BCD Counter Synchronous BCD counter: E.g.: 4-bit sync BCD counter w/ D-type f-f D 1 = 1 D D 2 = = D = ( + 4) Y = 1 8 J.J. Shann 7-4

41 E.g.: 4-bit sync BCD counter w/ T-type f-f T 1 = 1, T 2 = 8 1, T 4 = 2 1, T 8 = , y = 8 1 J.J. Shann 7-41

42 Three-decade BCD counter: J.J. Shann 7-42

43 Counter w/ Unused States n flip-flops 2 n binary states Unused states: states that are not used in specifying the sequential ckt may be treated as don t-care conditions or may be assigned specific next states Self-correcting counter: Ensure that when a ckt enter one of its unused states, it eventually goes into one of the valid states after one or more clock pulses so it can resume normal operation. Analyze the ckt to determine the next state from an unused state after it is designed. J.J. Shann 7-43

44 Example: The simplified f-f input eqs: D A = A B D B = C D C = B C Two unused states: 11 & 111 J.J. Shann 7-44

45 The logic diagram & state diagram of the ckt: Analysis * Self-correcting! J.J. Shann 7-45

46 7-12 Chapter Summary Registers Simplest register ( 7-1) Register with parallel load ( 7-1) Shift registers ( 7-6) Counters Ripple counter ( 7-6) Synchronous binary counters ( 7-6) Other counters ( 7-6) J.J. Shann 7-46