Derivation of State Graphs and Tables UNIT 14 DERIVATION OF STATE GRAPHS AND TABLES. Designing a Sequential Circuit. Sequence Detectors

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1 Derivation of State Graphs and Tables 2 Contents Case studies: sequence detectors Guidelines for construction of graphs Serial data code conversion Alphanumeric graph notation Reading Unit 4 Basic unit Unit : Latch & s UNIT 4 DERIVATION O STATE GRAPHS AND TLES Iris HuiRu Jiang Spring 2 Simple sequential Ckt Unit 2: Registers & Counters Complex sequential Ckt Units 35: SM Put it all together Unit 6: Summary Designing a Sequential Circuit 3 Given the specification of a sequential circuit Design procedure:. Construct a table or graph (Unit 4) 2. Simplify (Unit 5) 3. Derive input equations and output equations (Unit 2) 4 Sequence Detectors Basic unit Unit : Latch & s Simple sequential Ckt Unit 2: Registers & Counters Complex sequential Ckt Units 35: SM Put it all together Unit 6: Summary

2 Case I (/2) Case I (2/2) 5 Examine groups of 4 consecutive inputs & produce an output Reset after every 4 inputs e.g., = = Detector Observation: = S = Typical sequence / / Partial graph S / / / 6 Complete graph S S / / / / / / / / / / S 5 / / / / S 6 / Input/output Case II (/4) Case II (2/4) 7 / S Examine groups of 3 consecutive inputs & produce an output No reset e.g., = Detector = State graph (Mealy) S : initial, S : get, : get / S / S / / / S / S / / / / S / 8 S S State table = = S S S S S / A + B + = = S / S output = = = = / S / State maps / / S S / / / S / / / A + ='B B + = =A

3 9 Case II (3/4) State maps Case II (4/4) Moore? S : initial, S : get, : get, : get Realize it A + ='B Q: Check by yourself = =?? A' CK B + = A D =A B' CK B D S S S S = = S S S S S S output S S A + B + = = S Case III (/2) Case III (2/2) & detector Detector e.g., = a b c d e f = State assignment State for State for Complete 2 State for State for / S S S S / / / a / b / / / c / d / e /? S 5 / / i / Complete f S S b / / g / / / c e / / S 5 / / / h

4 3 Case IV (/2) Specifications = if total # of s is odd and at least two consecutive s have been received e.g., = =() State assignment Initial and for s State for s Reset or even s S S Odd s 4 Case IV (2/2) S Reset or even s State graph Initial and for s S Odd s S a S S e S IRIS H.R. JIANG f c g S 4 Even s Odd s d S 5 b 5 Guidelines for State Graph Construction 6 Guidelines for State Graphs Construction Steps. Construct sample sequences to help you understand the problem 2. Determine under what conditions it should reset 3. If only one or two sequences leads to a nonzero output, construct a partial graph Another way, determine what sequences or groups of sequences must be remembered by the circuit and set up s accordingly 4. Each time you add an arrow to the graph, determine whether it can go to one of the previously defined s or whether a new must added 5. Check your graph to make sure there is one and only one path leaving each for each combination of values of the input variables 6. When your graph is complete, verify it by applying the input sequences formulated in step

5 7 Serial Data Code Conversion 8 Serial Data Transmission Transmitter Bit Sequence Use 2 cables (not good) Serial Data Coding schemes Receiver Transmitter Serial Data Recovery Circuit Receiver NR NRI R Manchester bit time ; d ; ~d ; ; NR: Nonreturntozero NRI: Nonreturntozeroinverted R: Returntozero Mealy? NR data 2 Conversion Network Manchester data Moore? NR data 2 Conversion Network Manchester data 9 Mealy: Output depends on Current (synchronous) Input (maybe asynchronous) ewer s NR () S S = = S S S output () = = Bit sequence 2 S Moore: Output only depends on Current (synchronous) More s (in general) clock period delay S S S = = S S S output () / S / Manchester (ideal) 2 (NR) 2 / / S NR: combintaion of double s & double s State (Actual) S S S S S S S S S S S S Starting s: S, State S S S S S S S S S Starting : S clock period Glitch: false output clock period

6 Alphanumeric State Graph Notation 2 Alphanumeric State Graph Notation 22 When a sequential circuit has several inputs, label the graph arcs with alphanumeric input variable names instead of s and s 'R' e.g., 2 inputs: : forward, R: reverse R S R 'R S 'R R S 3 2 'R' 'R S 3 2 'R' Incomplete S S R = S S S S S S S S Output 2 3 Complete? Homework for Unit 4 23 Completely specified graph OR together all input labels on arcs emanating from a, the result can reduce to Cover all conditions: + 'R +'R' = + ' = AND together any pair of input labels on arcs emanating from a, the result can reduce to Only one arc is valid: 'R =, 'R' =, 'R 'R' = Notation in graph 'R' ' 4 / 2 3 / / / or any combination of input values 'R S 'R 24 Problems Homework #6: Units 34 Due am, June, 2; submit to ED58 Quiz #6: June 8, 2. 'R' 'R S 3 2 'R'

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