ITM1010 Computer and Communication Technologies

Transcription

1 ITM omputer and ommunication Technologies Lecture #5 Part I: Introduction to omputer Technologies K-Map, ombination and Sequential Logic ircuits

2 ITM 計算機與通訊技術 2 Product Product-Of Of-Sum onfiguration Sum onfiguration Direct extraction of POS from truth table: For each of F, write the corresponding term in the form of sum of complements of inputs. F equals the product of the sums. F B A ( )( )( )( )( )( ) B A B A B A B A B A B A F =

3 3-input K-mapK Layout of a 3-input K-map based on Gray ode ++ +B(A+A) +B() +B +++ B(A+A)+A(B+B) B()+A() B+A ITM 計算機與通訊技術 3

4 K-map: 4-input 4 example D D D D BD + D ITM 計算機與通訊技術 4

5 K-Map Minimization Guideline! Loop all isolated s;! onsider each remaining separately. If it can be looped in more than one way, try include it in the largest possible loop;! A minimal solution is derived as soon as all s are covered. In the process of making the largest loop, it is permissible to use previously covered s. ITM 計算機與通訊技術 5

6 lass Exercise Simplify the following logic function: D D D D ITM 計算機與通訊技術 6

7 Don t are ondition in K-MapK ertain combinations of inputs may be immaterial to a given function. For such don t care states the output is irrelevant and may be or. A A X X X don t care input condition B B B If we use X=, F = This can be simplified (with X=) to F = A + + With K-map, can be assigned to any don t care position to - form largest possible loop - ombine isolated to form a loop - In the example we can further simplify the expression by taking the bottom X as : F = + ITM 計算機與通訊技術 7

8 Design Example: Majority Detector Design a 4-input circuit that will function as a majority detector. The circuit should output high when a majority of the inputs are high. The first step is to complete a truth table and mark high outputs for every set of input conditions that contains three or four (majority) s. This is shown in the truth table on the right. A B D X ITM 計算機與通訊技術 8

9 Design Example: Majority Detector A B D X Next, plot the Boolean expression from the truth table on a K-map as shown and simplify the expression. D D D D X = D + BD + + AD ITM 計算機與通訊技術 9

10 Design Example: Majority Detector The simplified expression is shown on the right, which has four terms since four pairs of s can be looped on the K-map. Implementation is straightforward as shown on the right because this is an SOP expression. The circuit requires four 3-input AND gates and one 4-input OR gate. X = D + BD + + AD D AD BD ITM 計算機與通訊技術

11 Types of Digital Networks! ombinational: The logic outputs at each instant are determined only by the inputs at that instant! Sequential: The logic output are dependent on the previous inputs as well as the present inputs A F B When A=B=, F may be either or depending on the previous input. ITM 計算機與通訊技術

12 ommon ombinational Logic ircuits ITM 計算機與通訊技術 2

13 Encoder A circuit converts a signal to a coded format. Example: Decimal to Binary oded Decimal (BD) encoder Decimal signal lines BD b 3 b 2 b b ITM 計算機與通訊技術 3

14 BD Invalid Sum Detector Decimal signal lines BD Decimal signal lines Invalid BD b 3 b 2 b b b 3 b 2 b b Invalid BD numbers ITM 計算機與通訊技術 4

15 BD Invalid Sum Detector Invalid BD b 3 b 2 b b b 3 b 2 b 3 b 2 b 3 b 2 b 3 b 2 b b b b b b b b X = b 3 b 2 + b 3 b ITM 計算機與通訊技術 5

16 Multiplexer Select one signal from two or more input lines and transmit it on a single output line. Example: 2- multiplexer A select output B ITM 計算機與通訊技術 6

17 Multiplexer Example: n- multiplexer DEODER address I I 2 output I n n lines ITM 計算機與通訊技術 7

18 Demultiplexer Recover multiplexed signals and transmit them to separate outputs. e.g. 4-channel demultiplexer ITM 計算機與通訊技術 8

19 Half Adder Add 2 bits and produce both a sum and a carry output A B Sum arry A B Sum arry ITM 計算機與通訊技術 9

20 Full Adder Sum of three bits: 2 data bits and a carry bit from lower bit addition A B Sum out Sum A A B B B SUM = out A A B B B OUT = OUT = + B + A ITM 計算機與通訊技術 2

21 Building Full Adder from Half Adder A B HA S HA S Sum out ITM 計算機與通訊技術 2

22 Multi-bit adder circuits Parallel Adder Number of modules same as the word length ITM 計算機與通訊技術 22

23 Adder/Subtractor ITM 計算機與通訊技術 23

24 Sequential Logic ircuits ITM 計算機與通訊技術 24

25 Sequential Logic ircuits A sequential logic circuit s output depends on its previous state (condition) in addition to its current inputs. This is accomplished by using feedback from the circuit s outputs back to its inputs. A F B When A=B=, F may be either or depending on the previous input. ITM 計算機與通訊技術 25

26 Latch A latch circuit is a bistable device. Bistable indicates that the latch has two stable states. These two latch states are called the SET state and the LEAR state. Once a latch is put in one of these states it will remain in that state until forced to change states by another input signal. There are two basic types of latch circuits: the NAND-gate latch and the NOR-gate latch. ITM 計算機與通訊技術 26

27 NAND-gate Latch ITM 計算機與通訊技術 27

28 NOR-gate Latch ITM 計算機與通訊技術 28

29 Latches These latches are formed by using cross-coupled inverting logic gates. The cross coupling provides the feedback necessary for the latch circuit to retain (store) data. A latch constructed with NAND gates is referred to as an active-low latch, and a latch constructed with NOR gates is called an active-high latch. The active-low and active-high references are derived from the input logic level that must be applied to the latch to put it in a certain state. ITM 計算機與通訊技術 29

30 Latches A latch has two outputs. One is labeled Q. The other output, which is the complement of Q, is labeled Q. A latch can have only two valid output conditions. One is the SET state, where output Q = and Q =. The other condition is the LEAR state, where Q = and Q =. Since the latch is designed to normally have complementary outputs (Q and Q), it is only necessary to remember that Q is high in the SET state and Q is low in the LEAR state. ITM 計算機與通訊技術 3

31 Latches Q of course, will normally be the opposite level of Q, The Q output is a convenience for circuit designers, is often not used in digital circuits, and is sometimes not available as an output on a flipflop I. The LEAR state is also referred to as the RESET state. The latches are sometimes called S- (SET-LEAR) latches or S-R (SET- RESET) latches. Since a latch only has a SET state or a LEAR state, it can store only one bit of data. Latch circuits are typically used to store binary information on a temporary basis. ITM 計算機與通訊技術 3

32 State Table SET State A latch must be put in a SET state to store a binary data bit at the Q output. ITM 計算機與通訊技術 32

33 State Table LEAR State A latch must be put in a LEAR state to store a binary at the Q output. ITM 計算機與通訊技術 33

34 State Table RETAIN State The two logic s applied to this latch cause it to retain the condition it was in when the two inputs were brought high (inactive). ITM 計算機與通訊技術 34

35 State Table INVALID State For a NAND gate, s into each logic gate will produce a out of each gate. Equal outputs are considered INVALID. ITM 計算機與通訊技術 35

36 Active-Low Latch Operation ITM 計算機與通訊技術 36

37 Active-Low Latch ITM 計算機與通訊技術 37

38 Active-High Latch ITM 計算機與通訊技術 38