FPGA PUF Based on Programmable LUT Delays

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1 FPGA PUF Based on Programmable LUT Delays Bilal Habib Kris Gaj Jens-Peter Kaps Cryptographic Engineering Research Group (CERG) Department of ECE, Volgenau School of Engineering, George Mason University, Fairfax, VA, USA 16th Euromicro Conference on Digital System Design 2013 DSD 2013 B. Habib, K. Gaj, J.-P. Kaps FPGA PUF based on Programmable LUT Delays 1 / 20

2 Outline Introduction 1 Introduction DSD 2013 B. Habib, K. Gaj, J.-P. Kaps FPGA PUF based on Programmable LUT Delays 2 / 20

What is a Physical Unclonable Function Properties of PUFs Typical Ring-Oscillator (RO) PUF What is a Physical Unclonable Function (PUF) Challenge m bits PUF Response n bits n = f (m), nonlinear,

3 What is a Physical Unclonable Function Properties of PUFs Typical Ring-Oscillator (RO) PUF What is a Physical Unclonable Function (PUF) Challenge m bits PUF Response n bits n = f (m), nonlinear, unpredictable, one-way function. f is based on manufacturing variations unique for each chip. Tamper resistant: There is no secret that can be extracted. PUF produces a fingerprint for each chip. DSD 2013 B. Habib, K. Gaj, J.-P. Kaps FPGA PUF based on Programmable LUT Delays 3 / 20

4 What is a Physical Unclonable Function Properties of PUFs Typical Ring-Oscillator (RO) PUF What is a Physical Unclonable Function (PUF) Challenge m bits PUF Response n bits n = f (m), nonlinear, unpredictable, one-way function. f is based on manufacturing variations unique for each chip. Tamper resistant: There is no secret that can be extracted. PUF produces a fingerprint for each chip. Applications Chip identification Secret key generation IP Protection on FPGAs DSD 2013 B. Habib, K. Gaj, J.-P. Kaps FPGA PUF based on Programmable LUT Delays 3 / 20

5 Properties of PUFs Introduction What is a Physical Unclonable Function Properties of PUFs Typical Ring-Oscillator (RO) PUF Uniformity Percentage of 1 s in response (ideal: 50%) Uniqueness Inter-chip difference of responses (ideal: 100%) Bit-aliasing Number of bits different between 2 responses of different chips (ideal: 50%) Reliability Intra-chip similarity of responses (ideal: 100%) Steadiness Number of response bits that remain the same between responses to the same challenge (ideal: 100%) DSD 2013 B. Habib, K. Gaj, J.-P. Kaps FPGA PUF based on Programmable LUT Delays 4 / 20

6 Typical Ring-Oscillator (RO) PUF What is a Physical Unclonable Function Properties of PUFs Typical Ring-Oscillator (RO) PUF RO 1 RO 2 RO N MUX i MUX j 1 0 N 1 0 N counter counter >? Q challenge RO frequency difference depends on manufacturing variations. Output is 1 if frequency of RO i > frequency RO j. Routing from ROs to MUX does not need to be symmetrical. RO pairs with large frequency difference are less susceptible to noise. Potential Problems: Expensive in terms of Area, 1 bit per comparison Systematic variation DSD 2013 B. Habib, K. Gaj, J.-P. Kaps FPGA PUF based on Programmable LUT Delays 5 / 20

7 Programmable Ring Oscillators Programmable ROs Programmable RO PUF Layout Experimental Setup en Basic RO consists of 3 inverters and 1 AND gate. DSD 2013 B. Habib, K. Gaj, J.-P. Kaps FPGA PUF based on Programmable LUT Delays 6 / 20

8 Programmable Ring Oscillators Programmable ROs Programmable RO PUF Layout Experimental Setup Slice X1Y1 Slice X0Y0 Slice X0Y1 Slice X1Y0 en LUT LUT LUT LUT CLB Basic RO consists of 3 inverters and 1 AND gate. Using only 1 LUT per slice, 1 RO per CLB. DSD 2013 B. Habib, K. Gaj, J.-P. Kaps FPGA PUF based on Programmable LUT Delays 6 / 20

9 Programmable Ring Oscillators Programmable ROs Programmable RO PUF Layout Experimental Setup Slice X1Y1 Slice X0Y0 Slice X0Y1 Slice X1Y0 en 2 LUT 3 LUT 3 LUT 3 LUT CLB configuration Basic RO consists of 3 inverters and 1 AND gate. Using only 1 LUT per slice, 1 RO per CLB. Remaining 3 LUT inputs for configurations 8 configurations 8 frequencies per RO. DSD 2013 B. Habib, K. Gaj, J.-P. Kaps FPGA PUF based on Programmable LUT Delays 6 / 20

10 Programmable RO PUF Programmable ROs Programmable RO PUF Layout Experimental Setup new RO0 new RO1 1 0 RO counter en Control new ROr 1 M en Std counter 50 MHz log M 2 3 Only one RO active at a time they can t influence each other. To avoid correlations, only RO 0 RO 1, RO 1 RO 2,..., RO (r 2) RO (r 1) are compared. DSD 2013 B. Habib, K. Gaj, J.-P. Kaps FPGA PUF based on Programmable LUT Delays 7 / 20

11 FPGA Layout Introduction Programmable ROs Programmable RO PUF Layout Experimental Setup Device: Xilinx Spartan 3e, XC3S100. PUF with M=130 Ring Oscillators (13x10). Comparing M-1 rings Total bits = R128 R129 R0 DSD 2013 B. Habib, K. Gaj, J.-P. Kaps FPGA PUF based on Programmable LUT Delays 8 / 20

12 Logical Layout Introduction Programmable ROs Programmable RO PUF Layout Experimental Setup Comparison along the columns: P1 DSD 2013 B. Habib, K. Gaj, J.-P. Kaps FPGA PUF based on Programmable LUT Delays 9 / 20

13 Logical Layout Introduction Programmable ROs Programmable RO PUF Layout Experimental Setup Comparison along the columns: P1 Comparison along the rows: P2 DSD 2013 B. Habib, K. Gaj, J.-P. Kaps FPGA PUF based on Programmable LUT Delays 9 / 20

Experimental Setup Programmable ROs Programmable RO PUF Layout Experimental Setup 31 x Digilent Inc. Basys 2 Board. 130 ROs per PUF. 8 configurations per RO. Connected via USB to PC.

14 Experimental Setup Programmable ROs Programmable RO PUF Layout Experimental Setup 31 x Digilent Inc. Basys 2 Board. 130 ROs per PUF. 8 configurations per RO. Connected via USB to PC. Using Enhanced Parallel Port (EPP) protocol with Digilent Adept. Determined frequency of each configuration of each RO on each Chip. DSD 2013 B. Habib, K. Gaj, J.-P. Kaps FPGA PUF based on Programmable LUT Delays 10 / 20

and configurations for each board = 1.5 MHz DSD 2013 B. Habib, K.

15 Frequency Analysis Introduction Frequency Analysis Generating IDs Average board frequency = 165 MHz Standard Deviation amongst ROs and configurations for each board = 1.5 MHz DSD 2013 B. Habib, K. Gaj, J.-P. Kaps FPGA PUF based on Programmable LUT Delays 11 / 20

16 Frequency vs. RO Location Frequency Analysis Generating IDs Average Frequency of each RO in all configurations over 31 boards. DSD 2013 B. Habib, K. Gaj, J.-P. Kaps FPGA PUF based on Programmable LUT Delays 12 / 20

17 Random Within Die Variation Frequency Analysis Generating IDs Random with-in-die variation. Down Sample Moving Average (DSMA) with a 3x3 window. Normalized over F(0,0). DSD 2013 B. Habib, K. Gaj, J.-P. Kaps FPGA PUF based on Programmable LUT Delays 13 / 20

18 Random Within Die Variation Frequency Analysis Generating IDs Randomness Distribution Mean 0.0 Min % Max 2.27 % Peak to Peak 5.5% Standard Deviation 0.84% DSD 2013 B. Habib, K. Gaj, J.-P. Kaps FPGA PUF based on Programmable LUT Delays 14 / 20

19 Generating IDs - Crossover Frequency Analysis Generating IDs Frequencies of two neighboring ROs can cross. Response here is Not all RO pairs have a crossover. DSD 2013 B. Habib, K. Gaj, J.-P. Kaps FPGA PUF based on Programmable LUT Delays 15 / 20

20 Generating IDs Introduction Frequency Analysis Generating IDs Pseudo-code for ID Generation 1: if crossover then 2: if f > 150 MHz then {Thresholding Technique} 3: Contribute 8 bits towards an ID 4: end if 5: else 6: Determine 1 bit response by majority vote 7: end if Average Std. Deviation = 30 khz among 20 samples. Reliability requires no bit-flips. After applying Thresholding Technique a minimum of 283 strong bits remain amongst our PUFs on all 31 boards. DSD 2013 B. Habib, K. Gaj, J.-P. Kaps FPGA PUF based on Programmable LUT Delays 16 / 20

21 Results Introduction Result Comparison Conclusion and Future Work Slices % of total ROs 4x130= % Other Logic % Total % Ideal P1 P2 Uniformity 50 % 50.1 % 50.7 % Uniqueness 100 % 96.6 % 95.3 % Bit-aliasing 50 % 51.8 % 50.7 % Reliability 100 % 97.8 % 98.1 % Steadiness 100 % 99.5 % 99.5 % DSD 2013 B. Habib, K. Gaj, J.-P. Kaps FPGA PUF based on Programmable LUT Delays 17 / 20

22 Result Comparison Introduction Result Comparison Conclusion and Future Work Ideal P1 P2 Maiti Uniformity 50 % 50.1 % 50.7 % 50.5 % Uniqueness 100 % 96.6 % 95.3 % 93.9 % Bit-aliasing 50 % 51.8 % 50.7 % 50.5 % Reliability 100 % 97.8 % 98.1 % 99.1 % Steadiness 100 % 99.5 % 99.5 % 98.9 % DSD 2013 B. Habib, K. Gaj, J.-P. Kaps FPGA PUF based on Programmable LUT Delays 18 / 20

23 Result Comparison Introduction Result Comparison Conclusion and Future Work Ideal P1 P2 Maiti Uniformity 50 % 50.1 % 50.7 % 50.5 % Uniqueness 100 % 96.6 % 95.3 % 93.9 % Bit-aliasing 50 % 51.8 % 50.7 % 50.5 % Reliability 100 % 97.8 % 98.1 % 99.1 % Steadiness 100 % 99.5 % 99.5 % 98.9 % P1 P2 Maiti No. of Chips No. of Ring Oscillators Strong Response Bits Bits per Ring FPGA Device Spartan 3e Spartan 3e (XC3S100E) (XC3S500E) DSD 2013 B. Habib, K. Gaj, J.-P. Kaps FPGA PUF based on Programmable LUT Delays 18 / 20

24 Conclusion and Future Work Result Comparison Conclusion and Future Work Conclusions Programmable delays improve an RO PUF. Generate more than one stable random bit per RO on average. Systematic variation is canceled out. Locking of ROs is avoided. Compares well with state of the art RO PUF yet requires much less area. Future Work Subject our RO PUF to temperature and voltage variations. Analyze our PUF on newer devices. DSD 2013 B. Habib, K. Gaj, J.-P. Kaps FPGA PUF based on Programmable LUT Delays 19 / 20

25 Questions Introduction Result Comparison Conclusion and Future Work DSD 2013 B. Habib, K. Gaj, J.-P. Kaps FPGA PUF based on Programmable LUT Delays 20 / 20

Physical Unclonable Functions (PUFs) and Secure Processors. Srini Devadas Department of EECS and CSAIL Massachusetts Institute of Technology

Physical Unclonable Functions (PUFs) and Secure Processors Srini Devadas Department of EECS and CSAIL Massachusetts Institute of Technology 1 Security Challenges How to securely authenticate devices at