Bitline PUF:! Building Native Challenge-Response PUF Capability into Any SRAM. Daniel E. Holcomb Kevin Fu University of Michigan

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1 Sept 26, 24 Cryptographic Hardware and Embedded Systems Bitline PUF:! Building Native Challenge-Response PUF Capability into Any SRAM Daniel E. Holcomb Kevin Fu University of Michigan Acknowledgment: This work was supported in part by C-FAR, one of six centers of STARnet, a Semiconductor Research Corporation program sponsored by MARCO and DARPA, and by NSF CNS Any opinions, findings, conclusions, and recommendations expressed in these materials are those of the authors and do not necessarily reflect the views of the sponsors.

2 Context CMOS PUFs! Holcomb and Fu Bitline PUF CHES 24 2

3 Context CMOS PUFs! High-cost PUFs using custom circuitry Holcomb and Fu Bitline PUF CHES 24 2

4 Context! CMOS PUFs High-cost PUFs using custom circuitry Holcomb and Fu Low-cost PUFs using existing circuitry Bitline PUF CHES 24 2

5 Context! CMOS PUFs High-cost PUFs using custom circuitry Low-cost PUFs using existing circuitry This talk Holcomb and Fu Bitline PUF CHES 24 2

6 Contributions Word Word Word Y- Holcomb and Fu Bitline PUF CHES 24 3

7 Contributions Adding a few gates to wordline drivers of SRAM creates a new PUF Word Word Word Y- Holcomb and Fu Bitline PUF CHES 24 3

8 Contributions Adding a few gates to wordline drivers of SRAM creates a new PUF Word Enable Word Clk Reset Eval Word Y- Holcomb and Fu Bitline PUF CHES 24 3

9 Contributions Adding a few gates to wordline drivers of SRAM creates a new PUF Bitline PUF Challenge-response operation Low area overhead Simple Word Enable Word Clk Reset Eval Word Y- Holcomb and Fu Bitline PUF CHES 24 3

10 Outline. Introduction PUFs SRAM Bitline PUF 2. Evaluation Uniqueness Reliability Modeling Attacks 3. Summary and Related work Holcomb and Fu Bitline PUF CHES 24 4

11 Physical Unclonable Functions (PUFs) Map challenges to responses according to uncontrollable physical variations Unique to each chip and persistent Random dopant fluctuations and small devices Balanced parasitics and wire lengths to avoid bias Applications include anti-counterfeiting and hardware metering Challenges f Responses PUF Characterized by Challenge-Response Pairs (CRPs) Holcomb and Fu Bitline PUF CHES 24 5

12 6-Transistor SRAM Cell Ubiquitous memory Two stable states: (AB=) (AB=) Wordline selects a cell for reading/writing Complementary bitlines read/write values to/from selected cells wordline wordline A B A B bitlines BL BLB BL Holcomb and Fu Bitline PUF CHES 24 bitlines BLB 6

13 Reading an SRAM Cell Precharge Circuits Wordline Drivers Word Word Word Y- Sense Amps Holcomb and Fu Bitline PUF CHES 24 7

14 Reading an SRAM Cell Precharge Circuits P Wordline Drivers Word Word Word Y- WL Sense Amps BLi BLBi Holcomb and Fu Bitline PUF CHES 24 7

15 Reading an SRAM Cell Precharge Circuits P Wordline Drivers Word Word Word Y- WL Sense Amps BLi BLBi Holcomb and Fu Bitline PUF CHES 24 7

16 Reading an SRAM Cell Precharge Circuits P Wordline Drivers Word Word Word Y- WL Sense Amps BLi BLBi.2 Voltage.8.4 P! (Precharge) 2 3 Time [ns] Holcomb and Fu Bitline PUF CHES 24 7

17 Reading an SRAM Cell Precharge Circuits P Wordline Drivers Word Word Word Y- WL Sense Amps BLi BLBi.2 Voltage.8.4 P! (Precharge) WL! (Wordline) 2 3 Time [ns] Holcomb and Fu Bitline PUF CHES 24 7

18 Reading an SRAM Cell Precharge Circuits P Wordline Drivers Word Word Word Y- WL Sense Amps BLi BLBi.2 Voltage.8.4 P! (Precharge) WL! (Wordline)! (Read Enable) 2 3 Time [ns] Holcomb and Fu Bitline PUF CHES 24 7

19 Bitline PUF Accumulate wordline enable signals for concurrent read Concurrent reading causes contention Contention resolves according to variations Word Enable Clk Reset Eval Word Word Y- Holcomb and Fu Bitline PUF CHES 24 8

20 Bitline PUF Accumulate wordline enable signals for concurrent read Concurrent reading causes contention Contention resolves according to variations Word Enable Clk Reset Eval Word Word Y- Write SRAM cells Load WL Drivers Read Holcomb and Fu Bitline PUF CHES 24 8

21 Bitline PUF Accumulate wordline enable signals for concurrent read Concurrent reading causes contention Contention resolves according to variations Word Enable Clk Reset Eval Word Word Y- Write SRAM cells Load WL Drivers Read Holcomb and Fu Bitline PUF CHES 24 8

22 Reading a Bitline PUF Read with contention P Contention resolves according to variation WL WL BLi BLBi Write SRAM cells Load WL Drivers Read Holcomb and Fu Bitline PUF CHES 24 9

23 Reading a Bitline PUF Read with contention P Contention resolves according to variation WL WL BLi BLBi Holcomb and Fu Bitline PUF CHES 24 9

24 Reading a Bitline PUF Read with contention P Contention resolves according to variation WL WL BLi BLBi.2 Voltage.8.4 WL! WL 2 3 Time [ns] Holcomb and Fu Bitline PUF CHES 24 9

25 Reading a Bitline PUF Read with contention P Contention resolves according to variation WL WL BLi BLBi.2 Voltage.8.4 WL! WL 2 3 Time [ns] Holcomb and Fu Bitline PUF CHES 24 9

26 Reading a Bitline PUF Read with contention P Contention resolves according to variation WL WL BLi BLBi.2 Voltage.8.4 WL! WL 2 3 Time [ns] Holcomb and Fu Bitline PUF CHES 24 9

27 Reading a Bitline PUF Read with contention P Contention resolves according to variation WL WL BLi BLBi.2 Voltage.8.4 WL! WL 2 3 Time [ns] Holcomb and Fu Bitline PUF CHES 24 9

28 Reading a Bitline PUF Read with contention P Contention resolves according to variation WL WL BLi BLBi.2 Voltage.8.4 WL! WL 2 3 Time [ns] Holcomb and Fu Bitline PUF CHES 24 9

29 Reading a Bitline PUF Read with contention P Contention resolves according to variation WL WL BLi BLBi.2 Voltage.8.4 WL! WL 2 3 Time [ns] Holcomb and Fu Bitline PUF CHES 24 9

30 Reading a Bitline PUF Read with contention P Contention resolves according to variation WL Largely consistent over time for given column WL BLi BLBi.2 Voltage.8.4 WL! WL 2 3 Time [ns] Holcomb and Fu Bitline PUF CHES 24 9

31 Reading a Bitline PUF Read with contention P Contention resolves according to variation WL Largely consistent over time for given column WL BLi BLBi.2 Voltage.8.4 WL! WL 2 3 Time [ns] Holcomb and Fu Bitline PUF CHES 24 9

32 Reading a Bitline PUF Read with contention P Contention resolves according to variation WL Largely consistent over time for given column WL Varies across columns or chips BLi BLBi.2 Voltage.8.4 WL! WL 2 3 Time [ns] Holcomb and Fu Bitline PUF CHES 24 9

33 Challenge Response Pairs PUF Challenge: Y 4 possible challenges (Y = num. rows) For each cell in column:. wordline on, cell value 2. wordline on, cell value 3. wordline off, cell value 4. wordline off, cell value PUF Response: Value read by sense amp of column(s) Holcomb and Fu Bitline PUF CHES 24

34 Performance and Overhead Load Challenge Eval. Responses Write SRAM cells Load WL Drivers Read Y Cycles Y Cycles Cycle Word Word Word Y- Holcomb and Fu Bitline PUF CHES 24

35 Performance and Overhead Load Challenge Eval. Responses Write SRAM cells Load WL Drivers Read Y Cycles Y Cycles Cycle Word Word Word Y- Holcomb and Fu Bitline PUF CHES 24

36 Performance and Overhead Load Challenge Eval. Responses Write SRAM cells Load WL Drivers Read Y Cycles Y Cycles Cycle Word Word Word Y- Holcomb and Fu Bitline PUF CHES 24

37 Performance and Overhead Load Challenge Eval. Responses Write SRAM cells Load WL Drivers Read Y Cycles Y Cycles Cycle Word Word Word Y- Holcomb and Fu Bitline PUF CHES 24

38 Performance and Overhead Load Challenge Eval. Responses Write SRAM cells Load WL Drivers Read Y Cycles Y Cycles Cycle Word Word Word Y- Holcomb and Fu Bitline PUF CHES 24

39 Performance and Overhead Load Challenge Eval. Responses Write SRAM cells Load WL Drivers Read Y Cycles Y Cycles Cycle X X Word X X X Word X Word Y- Holcomb and Fu Bitline PUF CHES 24

40 Performance and Overhead Load Challenge Eval. Responses Write SRAM cells Load WL Drivers Read Y Cycles Y Cycles Cycle X X Word X X X Word X Word Y- Holcomb and Fu Bitline PUF CHES 24

41 Performance and Overhead Load Challenge Eval. Responses Write SRAM cells Load WL Drivers Read Y Cycles Y Cycles Cycle Word-parallel (e.g. 256 columns) Response latency X X Word X 6 cycles for 256-bit response as shown Depends on number of enabled rows X X Word X Word Y- Holcomb and Fu Bitline PUF CHES 24

42 Performance and Overhead Load Challenge Eval. Responses Write SRAM cells Load WL Drivers Read Y Cycles Y Cycles Cycle Word-parallel (e.g. 256 columns) Response latency 6 cycles for 256-bit response as shown Depends on number of enabled rows Area overhead A few extra gates per SRAM row Don t need to add circuitry on all rows X X X X Word Word X X Word Y- Holcomb and Fu Bitline PUF CHES 24

43 Integration Simple digital interface No power-cycling required Non-exclusive, SRAM rows still usable as memory when not used for PUF Does not upset stored data in non-used rows Word Enable Word Word Y- Clk Reset Eval Holcomb and Fu Bitline PUF CHES 24 2

44 Outline. Introduction PUFs SRAM Bitline PUF 2. Evaluation Uniqueness Reliability Modeling Attacks 3. Summary and Related work Holcomb and Fu Bitline PUF CHES 24 3

45 Methodology Circuit simulation using Ngspice Devices are 9nm Predictive Technology Model [] Sizing according to Nii et al. [2] Variation: threshold voltage and channel length [3,4] Noise: between cross-coupled nodes [5] n4 p2 n2 µ σ µ σ + + p n n3 experiment code available online: [] Predictive Technology Model. 9nm NMOS and PMOS BSIM4 Models! [2] Nii et al., IEEE Journal of Solid State Circuits, 24! [3] Pelgrom et al. IEEE Journal of Solid State Circuits, 989! [4] Seevinck et al. IEEE Journal of Solid State Circuits, 987! [5] Anis et al. Workshop on System-on-Chip for Real-Time Applications, 25 Holcomb and Fu Bitline PUF CHES 24 4

46 Choosing Useful Challenges Word Word Word Word Word Y- Word Y- Holcomb and Fu Bitline PUF CHES 24 5

47 Choosing Useful Challenges Word Word Word Word Word Y- Word Y- Holcomb and Fu Bitline PUF CHES 24 5

48 Choosing Useful Challenges Useful challenges have equal number of s and s Exponential subset of the 4 Y possible challenges Num. s in Challenge Num. s in Challenge 5% 4% 3% 2% % % Prob. of Diff. Response Num. of Challenges e+4 e+ e+6 e+2 equal / 2 Y Y (Num. of SRAM Rows) (Asymmetric designs may have different useful challenges) Holcomb and Fu Bitline PUF CHES 24 6

49 Uniqueness and Reliability Applying random challenges with equal number s and s Nominal conditions:.2v and 27 C Frequency Hamming Distance Between 32-bit Responses Within-Class Between-Class Holcomb and Fu Bitline PUF CHES 24 7

50 Uniqueness and Reliability Applying random challenges with equal number s and s Nominal conditions:.2v and 27 C Frequency.5.25 Nominal BER is 2.3% Hamming Distance Between 32-bit Responses Within-Class Between-Class Holcomb and Fu Bitline PUF CHES 24 7

51 Uniqueness and Reliability Applying random challenges with equal number s and s Nominal conditions:.2v and 27 C Frequency.5.25 Nominal BER is 2.3% Hamming Distance Between 32-bit Responses Within-Class Between-Class BER vs.2 V Supply Voltage [V] BER vs 27 C Temperature [C] Holcomb and Fu Bitline PUF CHES 24 7

52 Uniqueness and Reliability Applying random challenges with equal number s and s Nominal conditions:.2v and 27 C Frequency.5.25 Nominal BER is 2.3% Hamming Distance Between 32-bit Responses Within-Class Between-Class BER vs.2 V BER 7.6% across voltage and temperature Supply Voltage [V] BER vs 27 C Temperature [C] Holcomb and Fu Bitline PUF CHES 24 7

53 Modeling Attacks Can a model predict Bitline PUF s responses? (Yes) 3 2 Challenge values. WL on, value 2. WL on, value 3. WL off, value 4. WL off, value [] Joachims. Making large-scale SVM Learning Practical. Advances in Kernel Methods - Support Vector Learning, 999 Holcomb and Fu Bitline PUF CHES 24 8

54 Modeling Attacks Can a model predict Bitline PUF s responses? (Yes) 3 2 Challenge values. WL on, value 2. WL on, value 3. WL off, value 4. WL off, value [] Joachims. Making large-scale SVM Learning Practical. Advances in Kernel Methods - Support Vector Learning, 999 Holcomb and Fu Bitline PUF CHES 24 8

55 Modeling Attacks Can a model predict Bitline PUF s responses? (Yes) 3 2 Challenge values. WL on, value 2. WL on, value 3. WL off, value 4. WL off, value Prediction Accuracy % 9% 8% 7% 6% 5% Classification using SVM light [] PUF A PUF B PUF C Size of Training Set [] Joachims. Making large-scale SVM Learning Practical. Advances in Kernel Methods - Support Vector Learning, 999 Holcomb and Fu Bitline PUF CHES 24 8

56 Modeling Attacks Can a model predict Bitline PUF s responses? (Yes) 3 2 Challenge values. WL on, value 2. WL on, value 3. WL off, value 4. WL off, value CRPs must be obfuscated as usual (Mission Impossible?) Prediction Accuracy % 9% 8% 7% 6% 5% Classification using SVM light [] PUF A PUF B PUF C Size of Training Set [] Joachims. Making large-scale SVM Learning Practical. Advances in Kernel Methods - Support Vector Learning, 999 Holcomb and Fu Bitline PUF CHES 24 8

57 Outline. Introduction PUFs SRAM Bitline PUF 2. Evaluation Uniqueness Reliability Modeling Attacks 3. Summary and Related work Holcomb and Fu Bitline PUF CHES 24 9

58 Related Work SRAM PUFs [,2,3] Bistable-ring PUF [4] Low-power current PUF [5] [] Guajardo et al. CHES 27! [2] Holcomb et al. T-Comp 29! [3] Zheng et al. DAC 23! [4] Chen et al. HOST 2! [5] Majzoobi et al. ISCAS 2 Holcomb and Fu Bitline PUF CHES 24 2

59 Bitline PUF: Summary Modifying wordline drivers of SRAM array creates a new PUF with desirable properties Challenge-response operation Low area overhead Simple Enable Clk Reset Eval Load Challenge Eval. Responses Write SRAM cells Load WL Drivers Read Holcomb and Fu Bitline PUF CHES 24 2

60 Bitline PUF: Summary Questions? Modifying wordline drivers of SRAM array creates a new PUF with desirable properties Challenge-response operation Low area overhead Simple Enable Clk Reset Eval Load Challenge Eval. Responses Write SRAM cells Load WL Drivers Read Holcomb and Fu Bitline PUF CHES 24 2

61 Backup: Power Consumption Voltage Current [ua] Voltage Current [ua] V(P) V(WL) V() V(BL) V(BLB) I(VDD) Time [ns] Time [ns] Average Power [uw] SRAM Read Bitline PUF Eval Number of Rows Active in Challenge Holcomb and Fu Bitline PUF CHES 24 22

SRAM-based Physical Unclonable Functions

Feb 26, 25 @ Worcester Polytechnic Institute SRAM-based Physical Unclonable Functions Daniel E. Holcomb UMass Amherst Collaborators for these works: Wayne P Burleson Kevin Fu Amir Rahmati Uli Ruhrmair