The good, the bad and the statistical

Transcription

1 The good, the bad and the statistical Noel Menezes Strategic CAD Labs Design and Technology Solutions Intel Corp.

2 Acknowledgements Keith Bowman Yossi Abulafia Steve Burns Mahesh Ketkar Vivek De Jim Tschanz Chandra Kashyap Chirayu Amin Nagib Hakim

3 There are lies, damned lies, and statistics. -- Benjamin Disraeli

4 Variable vs. fixed frequency products Most parts viable # parts ASICs µps Target /Delay Microprocessors can be binned At-speed test is not economically feasible for most ASICs

5 Outline Statistical CD variation basics Modeling Path distributions The hope of SSTA Statistical optimization Statistical techniques in design Skew computation Min-delay analysis Bin-split prediction FMAX-ISB estimation Conclusions

6 Classification Electrical behavior Le VT Width Interconnect Spatial behavior Wafer to wafer Die to die Within die Total CD Variation Within-Die component Random component Within Wafer component Source: N. Hakim, ICCAD 2004

7 Scale of Variations Die-to to-die (D2D) Variations Systematic Within-Die (WID) Variations (Uncorrelated) Random Wafer Scale Die Scale Feature Scale

8 D2D variation Manufactured die D2D variation effects are primarily addressed by process engineers Le

9 Within-die (WID) variation Manufactured die Two WID components Purely random Correlated random -- systematic Le

10 Systematic (correlated random) WID variation sample sample 2 sample X% X% 2 +X% X% 5 6 -X% 5 6 -X% Models distance-dependent dependent smooth variations Exact shape is unknown S. Samaan, ICCAD 04

11 Nature of correlated variation P X X3 X X2 X X2 X2 X3 X3 X3 X X2 X P P X3 X2 L eff L eff ρ ij 0 Correlation Inter-Xtor distance L eff CDs of transistors that are close track Tracking diminishes with distance

12 Variations: Trend & Impact on Performance & Power Variation Delay Impact Power Impact Other Trend Leff Large Large Flat Width Small Small Decreasing Vt Small Medium SRAM Increasing Interconnect Small Low Increasing Other Variable Variable Flat N. Hakim, ICCAD 2004

13 Principle I: Path effect of random variations n cp σ = σ + σ + K + σ = T T T T cp nand nand nand ncp σ 2 T nand σt cp ncpσt nand = = Tcp ncptnand ncp σ Tnand Tnand

14 Principle II: Delay distributions for independent paths t chip = max ( t, ) t 2 t chip T = t T t2 T µ =, σ = PDF - PDF - 2 CDF P chip ( t T ) = P( t T ) P( t T ) chip Shift in mean CDF ( t ) = cdf ( t ) cdf ( t ) cdf chip 2

15 Chip-level delay distributions µ =, σ = t max Bowman, et al. ISSCC 200 As the number (N cp ) of independent critical paths increases, the WID distribution mean increases and the variance decreases As N cp increases to larger values, the dependency on N cp decreases

16 Combining the die-to to-die and within-die delay distributions 20 Normalized Probability Density WID Distribution D2D Distribution D2D WID: Ncp=00 D2D & WID: Ncp=00 D2D & WID Distribution Bowman, et al. ISSCC 200 Normalized Maximum Critical Path Delay Within-die variations impact the delay mean Die-to-die variations impact the delay variance

17 SSTA: Reduce pessimism of corner based analysis Assumption: Corner-based analysis is too pessimistic The deterministic worst-case corner is derived by simultaneously setting each parameter at its 3σ3 value Not correctly accounting for die-to to-die and within-die random and systematic components during cell characterization leads to unwarranted pessimism during STA σ Xtor = σ D 2 D + σsys + σ 2 rand Target timing corner

18 Recovery of random variation component by SSTA Worst-case process corner σ Xtor = σ D 2 D + σsys + σ 2 rand Target timing corner Worst-case product corner (potential) σ path = σ D 2 D + σsys + σ n rand cp ncp ncp σ rand The transistor-to to-path sigma reduction mitigates the the effect of random variations on product yield

19 The critical path effect on random variations µ =, σ = Required path std. dev. for 99% yield σpath t max 0 E+00 E+0 E+02 E+03 E+04 E+05 # paths The critical paths-to to-die timing pushout exacerbates the effect of random variations on product yield The pushout effect counters the path averaging effect on random variations

20 SSTA gain relative to 3σ3 corner analysis: Random σ rand /µ stage = % yield corner 3σ random corner.4 Overdesign factor σ gain = rand / Np Φ Y + σrand ncp Overdesign # chip-level paths # stages/path SSTA provides a potential gain relative to a 3σ3 corner-based STA for purely random variation

21 SSTA gain relative to 3σ3 corner analysis: Systematic WID variation Systematic WID affect all stages along a path equally no averaging effect due to path localization The number of systematic independent critical paths is determined by the spatial correlation distance Systematic WID -- sample Overdesign σWID sys gain = / Np + Φ Y σwid sys # paths SSTA gain relative to 3σ3 corner-based STA is reduced for systematic WID CD variation

22 The intelligent corner approach 99.9% yield corner Intelligent corner 3σ xtor corner Instead of SSTA, apply a global technique to pick a yield corner based on product information Number of critical paths Number of stages along critical paths Available process variation data Test methodology One such technique is described in Najm, Menezes [DAC 04]

23 Statistical optimization Differences in delay variations of different paths depend on the number and type of stages Due to differences in power sensitivity to delay, power can be improved by budgeting timing yield loss based on power sensitivity 3.2 n easy = 6 Normalized power Power - easy Power - hard CDF - easy CDF - hard CDF n hard = Path delay (ps) Burns, et al. DAC

24 Exploiting power sensitivities Target yield = 99% at 250ps.2 Normalized power 2.5 Easy path migration Hard path migration µ hard =!= µ easy Power - easy Power - hard CDF - easy CDF - hard CDF 0.5 Combined CDF Path delay (ps) Conventional optimization µ hard 200 ps 207 µ easy 200ps 92 Power (ave( ave.) Statistical optimization

25 Dashed iso-power level curves spaced at 2% intervals. The green locus represents those design targets that result in a 300ps median max delay The pink line shows design targets corresponding to some global guardband Statistical optimization benefits over global guardbanding Nominal Target Delay for Easy Paths (ps) Nominal Target Delay for Hard Paths (ps) N hard = 000 N easy =0000 Stage sigma = 5% p total = n hard p hard + n easy p easy Burns, et al. DAC 2007 Statistical optimization benefits are mitigated because the pushout effect for a large number of paths is not so pronounced

26 neasy =0000 nhard = 000 Power Benefit Sweeping Magnitude of Variation Easy stage sigma = sweeping Hard stage sigma = r*(easy stage sigma) Iso-hardware intensity. 0% Power Benefit of STAO -2% -4% -6% -8% -0% 0% 5% 0% 5% 20% Stage Sigma for Easy Paths r=.0 r=0.6 Burns, et al. DAC 2007

27 Statistics in design Min-delay analysis Max skew computation Bin split prediction Leakage-performance estimation

28 Basic timing checks: Hold check C G S Logic t logic D t CG + t logic t CS t hold min_ skew These are hard numbers in traditional STA This is statistically calculated

29 G Calculating min-delay skew C S Logic D P Xσ t logic ( t t t ) CGD where Xσ = CS hold f( DPM spec ) Xσ 0 t CGD - t CS The min-delay skew is calculated based on Number of min-delay paths on the chip Conservatism in hold characterization for sequentials Process variation spec at fast corner Sophistication of min-delay analysis methodology

30 Max skew computation Clock grid C Sampling path, CS Clock buffers G Clock-data path, CGD S D σ 2 m arg in 2 2 ( t ) + ( t ) 2cov( t, t ) = σ σ CS CGD Max delay skew (kσ( margin ) is based on CGD Testing methodology (binning?) Process variation specs at nominal and slow corners Conservatism in STA methodology Clocking and clock distribution methodology CS

31 FMAX prediction model 20 D2D Normalized Probability Density WID Distribution D2D Distribution WID: Ncp=00 D2D & WID: Ncp=00 D2D & WID Distribution Normalized Maximum Critical Path Delay Within-die variations impact the delay mean Die-to-die variations impact the delay variance

32 FMAX yield prediction Die-to-Die and Within-Die Process Variation Models Netlist of Critical Paths, Process File, Gate Location Statistical Circuit Simulator Die-to-Die Critical Path Delay Distribution Within-Die Critical Path Delay Distribution Critical Path Delay (s) Critical Path Delay (s) Bowman, et al., ISSCC 200

33 FMAX model comparison with a 0.25 µm m processor Cumulative Distribution (%) Measured Data Model Number of FMAX Standard Deviations Data represents ~50,000 die measurements taken at sort Bowman, et al., ISSCC 200

34 FMAX model comparison with a 0.3 µm m processor Cumulative Distribution (%) Model Measured Data V DD =.375V Temperature=80 C Process: 0.3µm Number of FMAX Standard Deviations Data represents ~,000 die measurements taken at class Bowman, et al., ISSCC 200

35 Individual Contributions of D2D and WID Variations Cumulative Distribution (%) Model: Only WID Variations Model: D2D & WID Variations Measured Data Model: D2D & WID Model: D2D Model: WID Number of FMAX Standard Deviations Model: Only D2D Variations Within-die variations primarily impact the FMAX mean Die-to-die variations primarily impact the FMAX variance Bowman, et al., ISSCC 200

36 MONTE-CARLO ITERATIONS FMAX-ISB prediction. Draw lots for process variation map 2. Map timing model onto variation map and recalculate path delay to find the slowest path that will define FMAX 3. Calculate the die's total leakage (ISB) FMAX is going to be defined by MANY paths (as a result of timing model re-order) The spatial distribution of the paths is very important to FMAX distribution sample sample 2 sample Abulafia, Kornfeld, Trans. VLSI X% -X% +X% -X% +X% -X%

37 I Leakage modeling speculated _die = i,j type= n, p I off (type,l i,j SF ) W i,j ( type) sample KX Slow FAST +X% -X% 0 Channel-length variation map Leakage map Abulafia, Kornfeld, Trans. VLSI 2005

38 FMAX/ISB prediction comparison with Si 02% 96% 90% 84% 78% 72% X 2X 3X This analysis predicts the log-normal distribution and BANANA shape Abulafia, Kornfeld, Trans. VLSI 2005

39 Design methdology µarch Custom Structural RTL TA TA Synthesizable RTL Synthesis Schematics TA Timing analysis TA Synthesis Layout TA TA APR Timing verification GAP The ROI from any fine-grained analysis flow like SSTA has to be justified in terms of the overall design methodology

40 Conclusion Statistical techniques are applied in design with good silicon correlation The application of statistical techniques at fine-grained circuit level i.e. SSTA may provide a benefit relative to a worst-case process corner approach for some products These benefits may not be large compared to an intelligent corner approach Statistical circuit optimization benefits are small A significant barrier to SSTA adoption is the impact on design methodology which has not been studied I am convinced that He is not throwing dice. Albert Einstein in a letter to Max Born, Dec. 2, 926 Many designers would prefer it that way

41 References K. Bowman, S. Duvall, J. Meindl, Impact of die-to to-die and within-die parameter fluctuations on the maximum clock frequency distribution, IEEE JSSC, 200. Y. Abulafia, A. Kornfeld, Estimation of FMAX/ISB in microprocessors, IEEE Trans. VLSI, S. B. Samaan, The impact of device parameter variations on the frequency and performance of VLSI chips, ICCAD S. Burns, M. Ketkar, N. Menezes, K. Bowman, J. Tschanz, V. De, Comparative analysis of conventional and statistical design techniques, DAC F. Najm, N. Menezes, Statistical timing analysis based on a timing yield model, DAC 2004.

42 Q & A