Lecture 20: Sequential Circuits. Sequencing

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1 Lecture 20: Sequential Circuits Sequencing Elements Simple /FF Timing efinitions Source: Ch 7 (W&H) Sequencing Use flip-flops to delay fast tokens so they move through exactly one stage each cycle. Inevitably adds some delay to the slow tokens Sequencing overhead Combinational logic output depends on current inputs Sequential logic output depends on current and previous inputs Called state or tokens Ex: FSM, pipeline in out Finite State Machine Pipeline 1

2 Sequencing Elements : Level sensitive a.k.a. Flip-flop: edge triggered a.k.a. Timing iagrams Flop (latch) (flop) esign Pass Transistor Pros Cons Used in 1970 s 2

3 3 esign Transmission gate - Inverting buffer X esign Tristate feedback Buffered input X X

4 4 esign Buffered output Widely used in standard cells X Flip-Flop esign Flip-flop is built as pair of back-to-back latches X X

5 Reset Force output low when asserted Synchronous vs. asynchronous Symbol Flop Synchronous Reset Asynchronous Reset Sequencing Methods Flip-flops 2-Phase es Pulsed es Flip-Flops Flop Flop 2-Phase Transparent es Pulsed es 1 2 p t pw p /2 Combinational Logic t nonoverlap Combinational Logic Half-Cycle 1 Half-Cycle 1 t nonoverlap p 5

6 Timing iagrams Contamination and Propagation elays A Combinational Logic Y A Y t cd t pd t pd t cd t setup thold Flop t ccq t ccq t pdq t ccq t setup t setup t cdq t pdq Max-elay: Flip-Flops F1 1 2 F2 t setup 1 t pd 2 6

EX T adder =590ps T result_mux =60ps T middle_bypass_mux =80ps T late_bypass_mux =70ps 2mm wire=100ps each T setup =62ps T hold =-10ps T pcq =90ps T pd =1000ps T C >10006290ps

7 EX T adder =590ps T result_mux =60ps T middle_bypass_mux =80ps T late_bypass_mux =70ps 2mm wire=100ps each T setup =62ps T hold =-10ps T pcq =90ps T pd =1000ps T C > ps Max elay: 2-Phase es tpd tpd1tpd 2 Tc 2tpdq sequencing overhead Combinational 2 2 Combinational 3 Logic 1 Logic 2 L1 L2 L t pdq1 1 t pd1 2 t pdq2 2 t pd2 3 7

8 Max elay: Pulsed es tpd Tc max tpdq, tpcq tsetup tpw sequencing overhead p p 1 L1 1 2 L2 2 1 t pdq (a) t pw > t setup 1 t pd 2 p (b) t pw < t setup 1 2 t pw tpd tsetup Min-elay: Flip-Flops < t ccq t cd t t t cd hold ccq F1 1 2 F2 1 t ccq t cd 2 8

9 Min-elay: 2-Phase es T hold <T nonoverlap t ccq d t t t t t cd1, cd 2 hold ccq nonoverlap 1 L L2 t nonoverlap 1 2 t ccq 1 t cd 2 Min-elay: Pulsed es p L1 t pw < t ccq t cd t t t t cd hold ccq pw 1 Hold time increased by pulse width p 2 L2 p tpw 1 t ccq t cd 2 9

10 In a flop-based system: Time Borrowing ata launches on one rising edge Must setup before next rising edge If it arrives late, system fails If it arrives early, time is wasted Flops have hard edges In a latch-based system ata can pass through latch while transparent Long cycle of logic can borrow time into next As long as each loop completes in one cycle Time Borrowing Example (a) Combinational Logic Borrowing time across half-cycle boundary Borrowing time across pipeline stage boundary 1 2 (b) Combinational Logic Loops may borrow time internally but must complete within the cycle 10

11 How Much Borrowing? 2-Phase es T borrow c setup nonoverlap t t t 2 Pulsed es t t t borrow pw setup L L2 2 t pw >t setup 1 2 t nonoverlap /2 Nominal Half-Cycle 1 elay t borrow t setup 2 Skew: Flip-Flops F1 1 2 F2 t T t t t pd c pcq setup skew sequencing overhead t skew t t t t cd hold ccq skew 1 2 t pdq t setup cq d >T skew F1 1 ecreases maximum propagation delay Increases minimum contamination delay 2 F2 t skew 1 t ccq 2 t cd 11

12 Skew: es 2-Phase es tpd Tc 2tpdq sequencing overhead t, t t t t t cd1 cd 2 hold ccq nonoverlap skew T t t t t 2 c borrow setup nonoverlap skew Combinational 2 2 Combinational 3 Logic 1 Logic 2 L1 Pulsed es t T max t, t t t t pd c pdq pcq setup pw skew sequencing overhead t t t t t cd hold pw ccq t t t t skew borrow pw setup skew L2 L3 3 Two-Phase Clocking If setup times are violated, reduce clock speed If hold times are violated, chip fails at any speed In this class, working chips are most important No tools to analyze clock skew An easy way to guarantee hold times is to use 2-phase latches with big nonoverlap times Call these clocks 1, 2 (ph1, ph2) 12

13 Summary Flip-Flops: Very easy to use, supported by all tools 2-Phase Transparent es: Lots of skew tolerance and time borrowing Pulsed es: Fast, some skew tol & borrow, hold time risk 13