How Computers Work Lecture 12

Transcription

1 How Computers Work Lecture 12 A Common Chore of College Life Introduction to Pipelining How Computers Work Lecture 12 Page 1 How Computers Work Lecture 12 Page 2 Page 1 1

2 Propagation Times Doing 1 Load Step 1: Step 2: Total Time = Tpd wash = Tpd dry = = How Computers Work Lecture 12 Page 3 How Computers Work Lecture 12 Page 4 Page 2 2

3 Step 1: Doing 2 Loads Combinational (Harvard) Method Doing 2 Loads Pipelined (MIT) Method Step 2: Total Time Step 1: Total Time Step 3: = Step 2: = = = Step 4: Step 3: How Computers Work Lecture 12 Page 5 How Computers Work Lecture 12 Page 6 Page 3 3

4 Doing N Loads Harvard Method: MIT Method: A Few Definitions Latency: Time for 1 object to pass through entire system. (= for Harvard laundry) (= for MIT laundry) Throughput: Rate of objects going through. (= for Harvard laundry) (= for MIT laundry) How Computers Work Lecture 12 Page 7 How Computers Work Lecture 12 Page 8 Page 4 4

5 A Computational Problem Add 4 Numbers: A B C D As a Combinational Circuit Tpd Tpd Throughput 1 / 2 Tpd Tpd Latency 2 Tpd A B C D How Computers Work Lecture 12 Page 9 How Computers Work Lecture 12 Page 10 Page 5 5

6 As a Pipelined Circuit Simplifying Assumptions Throughput Tpd Tpd Tpd clock Tpd clock Tpd 1 / Tpd Latency 2 Tpd clock Tpd clock 1. Synchronous inputs 2. Ts = Th = 0 Tpd c-q = 0 Tcd c-q = 0 How Computers Work Lecture 12 Page 11 How Computers Work Lecture 12 Page 12 Page 6 6

7 An Inhomogeneous Case (Combinational) An Inhomogeneous Case (Pipelined) Tpd = 2 * * Throughput Tpd = 2 * * Throughput Tpd = 1 1 / 3 Latency Tpd = 1 1 / 2 Latency 3 4 How Computers Work Lecture 12 Page 13 How Computers Work Lecture 12 Page 14 Page 7 7

8 How about this one? How MIT Students REALLY do Laundry (4) (4) * Comb. Latency 6 Comb. Throughput 1/6 Pipe. Latency 12 Pipe. Throughput 1/4 Steady State Throughput = Steady State Latency = How Computers Work Lecture 12 Page 15 How Computers Work Lecture 12 Page 16 Page 8 8

9 Interleaving (an alternative to Pipelining) Interleaving Parallel Circuits For N Units of delay Tpd, steady state Throughput N / Tpd Latency clk 1-4 sel x x x x Tpd How Computers Work Lecture 12 Page 17 How Computers Work Lecture 12 Page 18 Page 9 9

10 Definition of a Well-Formed Pipeline Same number of registers along path from any input to every computational unit Insures that every computational unit sees inputs IN PHASE Is true (non-obvious) whenever the # of registered between all inputs and all outputs is the same. Method for Forming Well-Formed Pipelines Add registers to system output at will Propagate registers from intermediate outputs to intermediate inputs, cloning registers as necessary. * (2) How Computers Work Lecture 12 Page 19 How Computers Work Lecture 12 Page 20 Page 10 10

11 Method for Maximizing Throughput Pipeline around longest latency element Pipeline around other sections with latency as large as possible, but <= longest latency element. * (2) Comb. Latency 5 Comb. Throughput 1/5 Pipe. Latency 6 Pipe. Throughput 1/2 How Computers Work Lecture 12 Page 21 A Few Questions Assuming a circuit is pipelined for optimum throughput with 0 delay registers, is the pipelined throughput always greater than or equal to the combinational throughput? A: Yes Is the pipelined latency ever less than combinational latency? A: No When is the pipelined latency equal to combinational latency? A: If contents of all pipeline stages have equal combinational latency How Computers Work Lecture 12 Page 22 Page 11 11

12 MIPS = Millions of Instructions Per Second Freq = Clock Frequency, MHz CPI = Clocks per Instruction CPU Performance Review: A Top-Down View of the Beta Architecture With st(ra,c,rc) : Mem[C<rc>] <- <ra> PC Q RA1 Memory RD1 XADDR JMP(R31,XADDR,XP) ISEL 0 1 MIPS = Freq CPI 1 31:26 OPCODE 25:21 20:5 9:5 4:0 RA C RB RC 0 1 To Increase MIPS: OPCODE RA1 Register File RD1 SEXT RA2 Register File RD2 1. DECREASE CPI. ASEL BSEL - RISC reduces CPI to CPI < 0? Tough... we ll see multiple instruction issue machines at end of term. Z FN A A op B B 2. INCREASE Freq. - Freq limited by delay along longest combinational path; hence RA2 Memory RD2 - PIPELINING is the key to improved performance through fast clocks. PCSEL WDSEL D PC WD Memory WA WE WEMEM WD Register File WA WE RC WE How Computers Work Lecture 12 Page 23 How Computers Work Lecture 12 Page 24 Page 12 12

13 Pipeline Stages Sketch of 4-Stage Pipeline Instruction Fetch GOAL: Maintain (nearly) 1.0 CPI, but increase clock speed. instruction APPROACH: structure processor as 4-stage pipeline: Instruction Fetch stage: Maintains PC, fetches one instruction per cycle and passes it to Register File stage: Reads source operands from register file, passes them to Register File instruction CL A (read) B stage: Performs indicated operation, passes result to CL Write-Back stage: writes result back into register file. Write Back instruction CL Y WHAT OTHER information do we have to pass down the pipeline? instruction (write) How Computers Work Lecture 12 Page 25 How Computers Work Lecture 12 Page 26 Page 13 13

14 PC Q RA1 Memory RD1 XADDR JMP(R31,XADDR,XP) Consider a sequence of instructions:... ADDC(r1, 1, r2) 4-Pipeline Parallelism 1 ISEL 31:26 OPCODE OPCODE :21 20:5 9:5 4:0 RA C RB RC 0 1 RA1 RA2 Register File Register SEXT RD1 RD2 File SUBC(r1, 1, r3) XOR(r1, r5, r1) MUL(r1, r2, r0)... Executed on our 4-stage pipeline: R2 Written R3 Written Z ASE L FN A A op B 0 B BSE L ADDC(r1,1,r2) SUBC(r1,1,r3) R1 Read R1 Read R1 Written R0 Written PCSE L 0 1 D PC WD Memory WA WE RA2 Memory RD WDSEL WD WA RC Register File WEMEM WE WE How Computers Work Lecture 12 Page 27 XOR(r1,r5,r1) MUL(r1,r2,r0) R1,R5 Read R1,R2 Read Time How Computers Work Lecture 12 Page 28 Page 14 14

15 BUT, consider instead: LOOP: ADD(r1, r2, r3) CMPLEC(r3, 100, r0) BT(r0, LOOP) XOR(r31, r31, r3) MUL(r1, r2, r2)... Pipeline Problems PROBLEM: Pipeline Hazards Contents of a register WRITTEN by instruction k is READ by instruction k1... before its stored in! EG: ADD(r1, r2, r3) CMPLEC(r3, 100, r0) MULC(r1, 100, r4) SUB(r1, r2, r5) fails since CMPLEC sees stale <r3>. R3 Written ADD(r1,r2,r3) ADD(r1,r2,r3) CMPLEC(r3,100,r0) CMPLEC(r3,100,r0) R3 Read BT(r0.LOOP) BT(r0.LOOP) XOR(r31,r31,r3) XOR(r31,r31,r3) MUL(r1,r2,r2) MUL(r1,r2,r2) Time Time How Computers Work Lecture 12 Page 29 How Computers Work Lecture 12 Page 30 Page 15 15

16 R3 Written ADD(r1,r2,r3) CMPLEC(r3,100,r0) SOLUTIONS: 2. Stall the pipeline. Freeze, stages for 2 cycles, inserting NOPs into IR... R3 Written CMPLEC(r3,100,r0) R3 Read ADD(r1,r2,r3) NOP SOLUTIONS: 1. Program around it.... document weirdo semantics, declare it a software problem. - Breaks sequential semantics! - Costs code efficiency. NOP CMPLEC(r3,100,r0) BT(r0.LOOP) R3 Read EXAMPLE: Rewrite ADD(r1, r2, r3) CMPLEC(r3, 100, r0) MULC(r1, 100, r4) as ADD(r1, r2, r3) MULC(r1, 100, r4) SUB(r1, r2, r5) XOR(r31,r31,r3) MUL(r1,r2,r2) SUB(r1, r2, r5) HOW OFTEN can we do this? CMPLEC(r3, 100, r0) How Computers Work Lecture 12 Page 31 DRAACK: SLOW How Computers Work Lecture 12 Page 32 Page 16 16

17 SOLUTIONS: 3. Bypass Paths. Add extra data paths & control logic to re-route data in problem cases. PC Q Hardware Implementation of Bypass Paths XADDR RA1 Memory RD1 JMP(R31,XADDR,XP) ISEL :26 25:21 20:5 9:5 4:0 OPCODE RA C RB RC <R1><R2> Produced 1 OPCODE RA1 Register File RD1 SEXT 0 1 RA2 Register RD2 File ADD(r1,r2,r3) CMPLEC(r3,100,r0) <R1><R2> Used BT(r0.LOOP) Z ASE L FN A A op B 0 B BSE L XOR(r31,r31,r3) RA2 Memory RD2 MUL(r1,r2,r2) PCSE L WDSEL How Computers Work Lecture 12 Page 33 D PC WD Memory WA WE WD WA RC Register File WEMEM WE WE How Computers Work Lecture 12 Page 34 Page 17 17

18 Next Time: Detailed Design of Bypass Paths Control Logic What to do when Bypass Paths Don t Work Branch Delays / Tradeoffs Load/Store Delays / Tradeoffs Multi-Stage Memory Pipeline How Computers Work Lecture 12 Page 35 Page 18 18