Practice 10: Ratioed Logic

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1 Practice 0: Ratioed Logic Digital Electronic Circuits Semester A 0

2 Ratioed vs. Non-Ratioed Standard CMOS is a non-ratioed logic family, because: The logic function will be correctly implemented regardless of device sizing. Device sizing will only affect the performance of the gate. A Ratioed gate is a circuit: That will only function properly if a certain ratio is maintained between the drive strengths of its components. If the required ratio is not met, the gate s output may be incorrect, the noise margins may become negative, or it may lose its regenerative property. February 5, 08

3 Why use ratioed circuits? Historically, before CMOS technology was available, it was hard to implement non-ratioed logic. Today, many techniques require ratioed circuits Such as SRAM design. Pseudo-nMOS is a ratioed logic family that requires less transistors than CMOS and can optimize one transition. 3 February 5, 08

4 Exercise : Pseudo nmos

5 Exercise a For a pseudo-nmos inverter with: A. Draw the gate s TC and compute noise margins Starting with in=0: M is cut-off M is in linear OH max.5 5 February 5, 08

6 Exercise a Raising in, M turns on in Saturation, while M is still linear: ISDp lin IDSn sat Wn 0.5 W p p SGp Tp SDp SDp n GSn Tn n DSn L p Ln 0.5 r p Tp out out p in Tn r out T in T in n r p d d out in in IL d r d in T in T in IL T T r r 6 February 5, 08

7 Exercise a IL T T r r Substituting values gives us: n r p p n r T IL T r r 97. OH min February 5, 08

8 Exercise a As in rises, out drops, causing M to enter linear and M to saturate: I sat I lin SDp DSn n r W Wn 0.5 p p SGp Tp p SDp n GSn Tn DSn DSn Lp L n p T p in T out 0.5 out r r out in T in T T p 8 February 5, 08

9 Exercise a r Differentiating, we find: out in T in T T dout d din d in r in IH in T in T T T IH T r 9 OL max February 5, 08

10 Exercise a Finally, we will find OLmin by setting in = =.5 M is still in linear and M is still saturated The equation we found before is still relevant: r out in T in T T min OL T in r February 5, 08

11 Exercise a Now we can draw the TC and find the Noise Margins NM H OH min IH NM L IL OL max OH max IL OH min IH OLmax OLmin February 5, 08

12 Exercise b B. Find the power dissipation with high and low inputs. How is this different than CMOS? I static p Tp OL min 65A P I 4.5W A static February 5, 08

13 Exercise c C. Find the high-to-low propagation delay of the gate, with an ideal step at the input. Assume a 0pF load is connected. Use the average current approximation, but differentiate between currents in different operating modes. At t<0, in=0, out= OHmax = At t=0, in, and the output starts to discharge: M saturation M linear This continues until: out = SGP - T = - T 3 February 5, 08

14 Exercise c Therefore we will find the current at: t=0 M:sat, M:lin t=t ( out = - T ) M:sat, M:lin t=t pd ( out = /) M:lin, M: lin t=0 GTn T I n 0 DSn T GTp T DSn DSp SAT LIN mA ISDp 0 4 February 5, 08

15 Exercise c t=t GTn T DSn T pinchoff n I DSn T T mA GTp T DSp 0.5 I SDp p T T T T LIN A 5 February 5, 08

16 Exercise c t=t pd GTn T DSn IDSn n T 0.5 LIN mA GTp T DSp LIN ISDp p T February 5, A

17 Exercise c I I ma t 0 n0 5 Calculate t -0: t 0 C 0.5 Calculate t pd -t : L It I n I p 4.9m mA Itpd Itpd, n Itpd, p 3.4m mA T I t o I t 0 p ps 4.95m pd t t C L 0.5 I T t I t pd 0 p m ns 7 February 5, 08