Modeling Logic Gates with Delay- Part#1

Transcription

1 Modelg Logic Gates with Delay- Part#1 by George Lungu - The previous series of tutorials treated logic gates ideally with considerg propagation delays, havg perfect edges at the put (negligible rise time and fall time) and with fite voltage ga (the gate fully switches for the slightest deviation of the put voltage around a threshold typically vdd/2). - The purpose of the models developed on this blog is not only educational but also utilitarian. We therefore try to obta teractive and animated models which are targeted to be fairly fast. While modelg a gate with all the aforementioned effects is fairly trivial Excel (especially by usg user defed functions), the model would become slow when these said models were to volve more than a half of dozen gates (as we could see one of the previous tutorials ab ideal logic gates). - In order to be able to conveniently simulate effects such as glitches combatorial logic (static and dynamic hazard), oscillation rg and relaxation oscillators, etc, with reasonable precision, we only need to troduce a propagation delay caused solely by rise or fall time (we actually consolidate propagation delay and edge delays a sgle effect sce we will apply the model to sgle-stage gates). This makes the model of a sgle-stage gate fairly simple and easy to program a sgle cell usg built- spreadsheet formulas (hence makg the model much faster than usg user defed functions). 1

2 The delay mechanism sgle-stage logic gates: - Let s consider the schematic of a isolated verter used the design of an tegrated circuit digital block and then let s connect it with other logic gates and see how we can model delays. -Let s also clude the parasitic capacitances which cause rise time and fall time delays. For any given logic gate the capacitance at the put of a gate is usually higher than its capacitance at its own put. The total capacitance at a logic gate put connected a circuit is the sum between it s own put capacitance and the put capacitance to the next stage (the latter usually domates). vdd vdd PMOS (pull up transistor) NMOS (pull down transistor) Drivg gate Co1 Ci2 Co2 Current gate Ci3 Driven gate (some arbitrary configuration) -Let s now consolidate a node capacitance to a total capacitance Ct vdd and attribute it to a the put of the drivg gate Co1+Ci2 Co2+Ci3 Drivg gate Current gate Driven gate 2

3 A Theven equivalent of a sgle-stage logic gate (verter): - After we consolidated the capacitances on each node, let s see how we can model an verter usg a Theven approximation. - With gettg to details you can read ab Theven s theorem and Theven equivalent circuits: - Besides the put capacitance, the put of the verter (or some other logic gate) has a very high impedance sce the put node is composed of two transistor gates which are isolated from the rest of the circuit. - The put can be modeled by a voltage source and a series resistor. Lookg at the static characteristic of an verter (the ones below were published by professor Bruce McNair from Stevens Institute of Technology bmcnair@stevens-tech.edu) we can see that for a typical gate the maximum ga (when put is around vdd/2 where both NMOS and PMOS transistors are saturation) is around the value of -20 (negative). The crowbar (short circuit) current for a small gate the modern CMOS process is ab 5uA -20uA around 2V supply which gives typical put resistances the range of hundreds of KW. - The values above are rough approximations. Besides, a CMOS logic gate has a Theven small signal put resistance that varies wildly dependg on the large signal value of the put (the transistors can be either a saturation, a triode regime, or a combation of both) but for the sake of buildg a high level model we can choose a number proportional to the size of the gate which produces the same delay as real gate connected the same conditions (same load capacitance) as the Excel gate. -Thgs get even more complicated for large capacitances or very fast edges due to the fact that the slew rate will completely cover any ga effects so the ga might be able to be replaced with negative fity which is actually good for us sce it simplifies the model. Static transfer characteristics of two different CMOS verters with different size ratios between N and P transistors (prof. Bruce McNair SIT) 3

4 The Theven equivalent (contuation): - Makg abstraction of the put capacitance for now, the equivalent put impedance (resistive) is fite. - The equivalent put resistance could be calibrated by benchmarkg real transient put waveform (or a precise V vdd/2 SPICE simulation) with the Excel model for a series of various size verters. For now we can consider it somewhere the range 100KW to 500KW.. - The ga for the put level around half the supply voltage is around -20 (26dB) for a typical modern CMOS gate, but with the caveat that the equivalent source voltage needs to be limited between and vdd. R G*V V vdd/2 - An equivalent model would be the one below which the comparator has a ga Ga_comp = G (ab 20) and, of course, its put is limited between and vdd. comparator - R + V V vdd/2 - Sce the ga is fairly high and the put signal has large and fast swgs around vdd/2 it might pay off (major model simplification and simulation speed improvement) to crease the ga of the comparator to fity hence replace the comparator with an ideal verter. - An extra argument for adoptg this model is the fact that realistic transient operation, due to the fast chargg of the put capacitance voltage by the logic gate, the slew rate effects weigh the ga effects (see next page for the simple model) =>>> 4

5 A simplified equivalent model: - We will use the model to the right, which (as we will see soon) can be written as a built- formula a sgle cell with the need to use very slow user defed functions =>>>>> - The problem with this model is that it can simulate rise time and fall time delays but no propagation delays. In order to simulate propagation delays we will need to cascade at least a couple of these models hence use at the least two cells of formulas. V Ideal Inverter Ga = - fity V_m = 0 V_max = vdd Threshold = vdd/2 R C - The aspect mentioned before is not much of a problem because as we can see the diagram below all the delay a simple (sglestage) gate is maly caused by rise time/fall time delays (t plh is ab half of the rise time). V A typical diagram explag the propagation delays and the edge delays (rise and fall time) for a generic gate 5

6 - Lookg aga at the simulated results of a modern CMOS verter (the ones here were published by professor Bruce McNair from Stevens Institute of Technology) we can see that, for a sharp put, the propagation delays are solely caused by edge delays. - For slopg puts thgs might be a little different but, aga the ga of a CMOS gate is high (around 20) and this must not affect the precision too much. - Besides, as mentioned before, an approximate model Excel could be benchmarked and calibrated agast a precision SPICE simulator if precision is important and it could be proven that the ma contributg factor the propagation delay for a simple gate is the slope delay. - In the figure to the right there is no practical or theoretical reason for the put not to start fallg at 2ns or start risg at exactly 8ns time. It might seems there is if we look at catalog sheets of verters sold commercially as stand-alone components (74HC series for stance), but we need not to forget that such parts have several stages (at least an additional put buffer plus one stage to compensate for the version of the buffer the case of an verter). For registers, counters, etc thgs are even worse sce such parts cannot be made with usg a tra of gates. In those cases the edge delay will be the native edge delay of the last stage (buffer) but the propagation delay will be due to a cumulative effect of the edge delays of the gates the critical path. A good example of this concept is a rg oscillator which has an obvious propagation delay between nonconsecutive stages but the edges of any stage put could be quite sharp. - The model formulas takg to consideration RC edge delay will be derived the next presentation. to be contued 6