Moving PUFs out of the lab

Size: px

Start display at page:

Download "Moving PUFs out of the lab"

Dayna Freeman
5 years ago
Views:

1 Moving PUFs out of the lab Patrick Schaumont 2/3/2012 Research results by Abhranil Maiti, Jeff Casarona, Luke McHale, Logan McDougall, Vikash Gunreddy, Michael Cantrell

2 What is a Physical Unclonable Function? A one-way function with a mapping determined by uncontrolled, but static, variations of a physical object Laser Input: Spot position Beam angle Sensor Output: Speckle Pattern sheet of paper 2

finite length The entropy of a PUF is the minimum

3 A Digital PUF Model 00 entropy The uncontrolled, static variations can be encoded as a bit-string of finite length The entropy of a PUF is the minimum length required to capture all variations of interest 3

4 A Digital PUF Model PUF Static Random Variable The (ideal) PUF is a static random variable The real world is not ideal! (more later) 4

5 PUF Applications PUF Static Random Variable ID L bits The (ideal) PUF is a static random variable Cryptographic Key Generation: Construct a secret L-bit vector out of the PUF static random variable 5

6 PUF Applications Challenge K bits PUF Static Random Variable ID L bits The (ideal) PUF is a static random variable Authentication: Generate an L-bit response out of a K-bit challenge using the PUF static random variable 6

7 A real PUF PUF Static Random Variable A real PUF is not a static random variable Noise Environmental parameters (temp, voltage) Aging Hence, some PUFs are better than others 7

8 Outline PUF Quality Metrics Design Space Quality Metrics Analysis PUF Aging Experiment Impact on Quality Metrics Conclusions 8

9 (Lots of) Silicon PUFs Name Entropy Year Arbiter PUF Edge Arrival Time 2004 Coating PUF Distribution of Parasitic Capacitance 2006 Ring Oscillator PUF Distribution of Frequencies 2007 SRAM PUF Startup Value of Bit Cells 2007 Butterfly PUF Race condition in S/R Flip-Flop 2009 Glitch PUF Glitch Timing in Combinational Logic 2010 Mecca PUF Write Failure in SRAM Bit Cell

10 Classification of Silicon PUFs Intrinsic* PUFs Entropy harvesting based on circuit startup or circuit failure Circuit can be reused in normal operating conditions Non-intrinsic PUFs Entropy harvesting under regular operating conditions These circuits are dedicated * Not a commonly agreed-upon definition; but makes most sense 10

11 (Lots of) Silicon PUFs Name Entropy Year Arbiter PUF Edge Arrival Time 2004 Coating PUF Distribution of Parasitic Capacitance 2006 Ring Oscillator PUF Distribution of Frequencies 2007 SRAM PUF Startup Value of Bit Cells 2007 Butterfly PUF Race condition in S/R Flip-Flop 2009 Glitch PUF Glitch Timing in Combinational Logic 2010 Mecca PUF Write Failure in SRAM Bit Cell 2011 Intrinsic Non-Intrinsic 11

12 Estimating PUF Quality PUF Challenge K bits ID Static L bits Random Variable SRAM PUF? Arbiter PUF? RO PUF? Mecca PUF? How to select among x PUF designs with roughly the same I/O? (K, L bits) How to decide which provides a better source of static entropy? 12

13 The PUF Quality Design Space We cannot measure entropy directly, but we can estimate it by measuring a large amount of devices Analyze PUF responses in a four-dimensional space: Chip index (N) Bit index in a ID (L) Measurement index for each ID (T) Bit index in challenge (K) This proposal only concerns the source of entropy; it does not cover area cost, performance 13

14 Starting point: Measuring PUFs ECE VT students use a prototyping FPGA board with a unique serial number We measured, over 2 years, 193 of these boards, each configured with an RO PUF 14

15 How to Encourage Data Collection 15

16 Measurements Database chips, one PUF per chip, 512 RO s per PUF, 100 measurements per PUF N = 193, L = 512, T = 100, K = NA 16

17 First Impression Average Frequency of each RO over 125 FPGAs 17

18 7 Metrics Characterize Design Space Population Uniqueness Probability of Misclassification Identifier Uniformity Bit Aliasing Stability Reliability Steadiness Challenge/Response Diffuseness Based on proposals by Maiti, Hori, Su, ao. 18

19 7 Metrics Characterize Design Space Population Uniqueness Probability of Misclassification Identifier Uniformity Bit Aliasing Stability Reliability Steadiness Challenge/Response Diffuseness Based on proposals by Maiti, Hori, Su, ao. 19

20 Metrics characterizing chip population Uniqueness K N L T Average Hamming Distance between IDs (over K, L, N) Expect 50% 20

21 Metrics characterizing chip identifier Uniformity (of chip i) K N L T All Devices N All Challenges K Average Hamming Weight of Identifier Bits Expect 50% 21

22 Metrics characterizing chip identifier Bit Aliasing K N L T All Devices N All Challenges K Average Hamming Weight of bit i from L, averaged over all identifiers Expect 50% 22

Metrics characterizing chip identifier Bit Aliasing K N L T All Devices N All Challenges K 0.8 0.6 0.

23 Metrics characterizing chip identifier Bit Aliasing K N L T All Devices N All Challenges K Average Hamming Weight of bit i from L, averaged over all identifiers

24 Practical Comparisons RO-PUF Spartan 3E 90nm Arbiter PUF Virtex 5 65nm N=193 chips L=512-bit ID T=100 Meas/ID K=1 ID/Chip N=45 chips L=128-bit ID T=1024 Meas/ID K=1024 ID/Chip Virginia Tech AIST, JP oh/sasebo/en/index.html 24

25 Comparative Analysis Arbiter PUF Ring Osc PUF Ideal PUF Uniqueness* 36.7% 94.1% 100% PMSID Uniformity 55.7% 50.6% 100% Bit Aliasing 19.6% 50.6% 50% Reliability 99.8% 99.1% 100% Steadiness 98.5% 98.5% 100% Diffuseness 98.4% - 100% * Scaled to 100% 25

26 Sample Size is Important Confidence is proportional to /sqrt(n) Arbiter PUF Ring Osc PUF Uniqueness 36.7% ± 15.4% 94.1% ± 1.5% Uniformity 55.7% ± 0.3% 50.6% ± 0.2% Steadiness 98.5% ± 2.1% 98.5% ± 0.05% Two-sided 95% confidence 26

27 Outline PUF Quality Metrics Design Space Quality Metrics Analysis PUF Aging Experiment Impact on Quality Metrics Conclusions 27

28 Stability issues: PUF Aging PUF PUF Static Random Variable Static Random Variable Aging induces permanent electrical changes Slower transistors, lower drive capability (NBTI, HCI, TDDB) Wires degrade or fail (Electromigration) 28

How to test aging effects Simulated by heating/overpowering Eg. MIL-STD-883G 1005.

29 How to test aging effects Simulated by heating/overpowering Eg. MIL-STD-883G C shorter at higher temperatures, at specified bias Thermal Chamber 29

30 Experimental Setup T Stress V Stress Nominal V 1.2V V Stress 1.5V/1.8V Room Temperature 1 2 Temperature Stress (70C/80C)

31 What to expect? PDF HD 31

32 Impact on Oscillation Frequency V stress impact more substantial 32

33 Impact on Oscillation Frequency Frequency of 512 RO s under T + V Stress 33

34 Significant Impact on Reliability 34

35 Impact on Uniqueness Since Uniqueness is a property of a population, a model for frequency change is needed Frequency of oscillator j in chip i Average Frequency of Population Static Process Variations Variations Due to Aging Variations Due to Noise Derived from Measurement Database (N chips) Derived from Aging Experiment (1 chip) 35

36 Distribution of average frequency of 512 RO s after aging Aging after 400Hrs with T+V stress (Location-independent) Simulated Aging (Average, StdDev) 36

37 Distribution of variations over 100 repeated measurements Results in zero-mean normal distribution Aging + Noise distributions enable simulation of aging effects Aged Frequency Chip i Oscillator j = Population Average Static Deviation Chip i Oscillator j N( aging, aging ) N(, noise_after_aging ) 37

38 Aging Results for 178 FPGA s Uniqueness for a population of 178 FPGA s after aging Average Min Max Std Original V-stress 200 Hrs V-stress 400 Hrs T+V-stress 200 Hrs T+V-stress 400 Hrs Almost no impact! 38

39 Conclusions 4 dimensions characterize PUF quality Population Identifier Stability Challenge/Response Quality factors determined empirically PUFs grow old Impact on reliability is significant Impact on uniqueness is marginal 39

40 References A. Maiti et al, A Large Scale Characterization of RO PUF, HOST 2010 A. Maiti et al, The Impact of Aging on an FPGA-based Physical Unclonable Function, FPL 2011 A. Maiti et al, A Systematic Method to evaluate and Compare the Performance of Physical Unclonable Functions, IACR eprint 2011/657 Y. Su et al, A Digital 1.6 pj/bit chip identification circuit using Process Variations, JSSCC 43(1):69-77, Y. Hori et al, Quantitative and statistical performance evaluation of arbiter PUFs on FPGAs, RECONFIG 2010 R. Maes, I. Verbauwhede, Physically Unclonable Functions: A Study on the State of the Art and Future Research Directions, Springer,

41 41

Employing Process Variation for Building Chip Identifiers

Turning Lemons into Lemonade: Employing Process Variation for Building Chip Identifiers Leyla Nazhandali, Electrical and Computer Eng. Department Virginia Tech Outline Part 1: What are PUFs? Identity of