CGTA: Current Gain-based Timing Analysis for Logic Cells

Transcription

1 GTA: urrent Ga-based Timg Analysis for Logic ells S. Nazarian, M. Pedram University of Shern alifornia EE-Systems, Los Angeles A T. L, E. Tuncer Magma Design Automation Santa lara, A 95054

2 rosstalk-aware Logic ell (Gate) Timg Analysis Background Gate-level timg analysis tools such as STA and SSTA tools are used as efficient alternatives to Spice with an acceptable level of accuracy In many timg analysis tools, large errors can be observed when crosstalk noise is present Example: Static Timg Analysis (STA) T R m T R max A R m A R max T F m T F max A F m A F max c c A F m A F max A F m A F max T F m T F max T F m T F max 2

3 Motivation Stage Delay Interconnect Delay Logic ell (Gate) Delay _x _x INV x R sub1_x R sub 2_x _u R 4INV x _u 16INV x 64INV x _y _y INV y m m m R R R sub 1_y sub 2_y 4INV 16INV y y _v _v 64INV y ircuit (Timg) Delay Analysis STA and SSTA tools 3

4 rosstalk-aware Logic ell Timg Analysis Motivation STA/SSTA tools utilize delay models for both terconnections and logic cells The function of a cell delay model is to take an put (which may be subjected to couplg noise) waveform and produce the waveform for the cell put This process is known as the cell delay or (timg) analysis Two ma classes of techniques 1.Voltage-based techniques 2.urrent-based techniques 4

5 Voltage-based ell Delay Modelg onventional cell delay analysis tools are accurate, maly due to approximation of put with a saturated ramp, i.e., eff eff onventional (voltage-based) cell delay analyzers Ouput (Hspice ) Noisy put eff (E4) eff Equivalent put (E4) 1.00E E E E E E-09 The larger the number of 0.5V dd crossg pots, the large the pessimism can be 5

6 Non-voltage-based ell Delay Modelg Equation-based: haracterization of real silicon to equation-based models is not generally feasible v ell i Y(s) urrent-based is more accurate than voltage-based modelg, esp. considerg the impact of the shape of a noisy waveform Motivation for the proposed current-based model: The existg current-based cell delay models are too complex to use a AD tool 6

7 Existg urrent-based Models v ell i Y(s) Keller et al model: i I ( V, V ) g ( v, v ) v t M ( v, v ) v t Miller capacitor M = Internal parasitic (to ground) capacitor g = + A 2-D lookup table is used to store values of I(V, V ) which are found through a series of D Spicebase simulations M and g are assumed to be constant and calculated through a series of transient simulations with voltage transitions applied at the put and put nodes, durg which the current flowg through the put node is measured 7

8 urrent-based Models (ont d) Keller et al model is the most accurate current-based model; however, it is too complex to be utilized existg AD tools and flows Blade is a simpler model with M (or ) set to 0 omplexity is maly due to the dependence on put voltage 8

9 Our GTA ell Delay Model urrent Ga Goal: Given a (noisy) voltage waveform at the cell put, determe the put voltage waveform which has m error w.r.t. the actual put waveform learly, the put voltage of a cell is a function of the put voltage, the put parasitic capacitances, the put load, and V dd We defe the current ga, c, as the derivative of the put current to the put voltage, i.e., i v 1.10E E E E E E-01 v i c 0 1E-09 2E-09 3E-09 4E-09 v ell i Y(s) 9

10 I ga Table Each logic cell a standard cell library is precharacterized with an I ga (K L) lookup table ( V, ) ( i, j) i j c eff c v v ( t) V (.,.) 0 if v 0 c i i v ell i Y(s) I ga Table 1 eff 2 eff j eff L eff 1 v 2 v. i v. K v c ( i, j) 10

11 Output Voltage alculation 1 ' 2 i ( tk 1) i ( tk) c( tk) v ( tk 1) ( t ){ ( 1)} c k v tk 2 1 ( n1) n... ( t ){ ( 1)} c k v tk n! i (t 0 ) is itialized to zero. c (t k ) is a shorthand notation for c (v (t k )) c (v (t k )) is found from the I ga table, possibly by terpolation ( n 1) ( t ) ( n 1) ( t ) n i ( t ) c c k n k n k is the n th order current ga, v v which is calculated directly durg the itial characterization process or is approximated from entries the I ga In practice n=1 (or 2) is sufficient for accurate timg analysis of a logic cell subjected to a noiseless ramp (or a noisy put waveform); t= t k+1 -t k is the samplg time Note that the P computed put values may not be equidistant. A set of P equidistant pots are computed based on weighted average of the two nearest values found by Taylor expansion 11

12 An Example Result of the GTA Model v (Hspice) v (GTA) v i (GTA) i (Hspice) E+00 1.E-09 2.E-09 3.E-09 4.E-09 12

13 GTA ell Timg Analyzer Experimental Results (Hspice) E E E E E E-10 2.E-09 3.E-09 5.E-09 6.E-09 8.E-09 Size of the I ga table: (20,5) omparison with Hspice: the put voltage waveforms generated by the GTA delay calculator matched Hspice-produced waveforms with only a 1-3% error 13

14 onventional ell Delay Modelg Fd an equivalent put le, eff, such that when it is applied to the put of a cell, it generates an put waveform that matches the actual waveform terms of its arrival time and transition time v v (Hspice) v eff eff 4.E-09 4.E-09 5.E-09 5.E-09 6.E-09 6.E-09 14

15 Existg ell Delay Analyzers Pot-based Noisy approximations pot-based approximation Noiseless Pot-based: eff slew is set to the time from 0.1V dd to 0.9V dd crossg pots of the put waveform as if it had not been affected by noise Noisy Pot-based: eff slew is set to the time 0.2 from 0.1V dd to 0.9V dd pots of put waveform P1 and P2 set the 0.5V dd of eff to the latest 0.5V dd 4E E-09 5E E-09 6E E-09 7E-09 crossg pot of the put waveform Least Square Fit approximations Least Square Fittg (LSF): eff is the best least square lear fit of the noisy put waveform t 90 t 10 % % { v noisy ( t k ) ( a t k b )} 2 15

16 Existg ell Delay Analyzers (cont.) LSF approximations (cont.) Weighted LSF t 90 t 10 % Elmore-based % { noiseless ( t k )( v noisy Slope of the le is selected such that the area, which is encapsulated by that le and v 1 (t) = 0.5V dd, v 2 (t) = V dd, is equal to the area surrounded between the noisy put and les v 1 and v 2 ( t k ) ( a t k b )) 2 16

17 Experimental Setup For both configurations we set the arrival time and slew (transition time) of the victim le put to 1000ps and 150ps. onfiguration I is a pair of 1000m coupled terconnect les runng parallel to one another with a total distributed couplg value of 100fF. Both aggressor and victim le puts have a slew of 150ps. For configuration I we swept the arrival time of the aggressor le put from 500 to 1500ps steps of 5ps. onfiguration II cludes two aggressor les each with 100fF total couplg and a victim, all of which are 500m long. We mataed a fixed offset of -100ps between signal arrival time of the 1st and 2nd aggressor le puts, while sweepg that of the 2nd aggressor le put arrival time. The two aggressor puts have slews 200ps, and 400ps, respectively. 17

18 urrent-based ell Delay Analysis - Experimental Results 100fF 100fF 100fF Method Noiseless-Pot-based Noisy Pot-based Least Square Fittg (LSF) ~ Runtime per case (sec) Delay error (psec) = delay Hspice delay method onfiguration I onfiguration II Max Avg Max Avg Elmore-based [Nazarian] Weighted LSF [Hashimoto] GTA All cells fr om a TSM 130nm, 1.2Vpr oduction cell libr ar y rosstalk noise pulse amplitude of less than 0.36V (i.e., 30% of V dd ) 18

19 onclusions The GTA logic cell timg analyzer was presented to address the complexity issue with the existg current-based cell delay models A pre-characterized table of current ga of i to V and values is utilized combation with the Taylor series expansion to progressively compute the put current waveform The put voltage is then produced by tegratg the put current Experimental results show the accuracy and efficiency of this new delay model 19

20 BAKUP SLIDES

21 Logic ell and Interconnect Delay Analysis Stage Delay Interconnect Delay Logic ell Delay _x _x INV x R sub1_x R sub 2_x _u R 4INV x _u 16INV x 64INV x _y _y INV y R m m m sub 1_y R sub 2_y The function of a cell delay model is to take an put (subjected to noise) waveform and produce the waveform for the cell put This process is known as the cell delay 21 or (timg) analysis R 4INV 16INV y y _v _v 64INV y

22 onventional Pre-haracterization v ell R 1 2 eff v ell Y(s) eff 1 Tr 2 Tr. j Tr. M Tr 1 eff 2 eff i eff T r ( i, j ), o u t d ela y ( i, j ) N eff 22

23 omplexity Analysis All conventional gate delay propagation techniques can determe the required crossg pots for the waveforms such as the 0.5Vdd crossg pots O(P) time They can all apply closed form formulas (e.g. the one for LSF) to fd the coefficients a and b for eff O(P), because the closed form formulas consist of several summations over P WLS has an additional (characterization step to calculate the weightg factor the LSF formula which is likewise of order O(P) haracterization process: GTA needs to estimate c which is also of order O(size(I ga )) Taylor expansion also has the complexity of O(P) ) GTA-based cell delay analysis technique takes O(P) to calculate current To compute the put voltage the tegration takes O(P) Hence, the worst case complexity of GTA (similar to that of the conventional voltage-based techniques) is O(P 23

24 GTA-based ell Delay Model Experimental Results (Hspice) 0 4E E-09 5E E-09 6E E-09 7E , 200, and 220fF of couplg capacitances exists and the signal transitions on aggressor les occur close enough to create large crosstalk-duced fluctuations around 0.5V dd level and hence cause multiple 0.5V dd crossg pots at the put of the victim Although the error 0.5V dd propagation delay value is quite low (less than 1%,) it is seen that the equivalent put waveform does not match the Hspice waveform as close as those parts (a) and (b) 24

25 Weighted LSF alculation Steps (Step I) Fd the derivative for the noiseless put: noiseless noiseless noiseless v ( t) v ( t ) v ( t ) v noiseless noiseless alculate the noiseless critical region [t 10%, t 90% ] noiseless is non-zero only for pots the noiseless critical region; otherwise it is set to zero ( t) ( t) dt dt t 10 % t 90 % noiseless v noiseless v 0.2 noiseless 0 4.E-09 5.E-09 5.E-09 6.E-09 6.E-09 25

26 Weighted LSF alculation Steps (Step II) Determg eff : M P 1 k0 { noiseless ( t k )( v noisy ( t k ) ( a t k b)) 2 } t 10 % t 90 % 26