13 Combinational Logic Devices

Transcription

1 Prof. r. J. Reichardt Prof. r.. Schwarz F Elektrotechnik/Informatik ombinational ogic evices Purpose of combinational logic design: uilding larger, more sophisticated logic circuits by using adaptable and versatile blocks which are commercially available. In order to reduce the number of packages it is necesasary to avoid using discrete gates. More frequently the designer will apply programmable Is which can enlarge the integration of several building blocks into one larger package. ence handling errors with interfacing and soldering can be avoided. uilding blocks perform a variety of tasks: ogical and arithmetical data manipulation (comparators, adders) ata selection from various sources (multiplexers, priority encoders) evice selection and data distribution to various destinations (decoders, demultiplexers) ode conversion, parity generation (code converters) Error detection (parity detectors) pplied technology: VSI (very large scale integrated) circuits with up to millions of gates (N, OR, NN, NOR). igital ircuits I -

2 Prof. r. J. Reichardt Prof. r.. Schwarz F Elektrotechnik/Informatik. Multiplexer (ata Selector/Switch) Multiplexers perform the function of selecting one of many data input lines for transmission to some destination. It requires n data select lines to control n data input lines. Thus a MU is a n input / output device. Single 8-ine to -ine ual -ine to -ine Quadruple -ine to -ine igital ircuits I -

3 Prof. r. J. Reichardt Prof. r.. Schwarz F Elektrotechnik/Informatik Example: - to -Multiplexer Truth table with entered signal representation E S S Y I I I I S S I E I E S I E I E S ogic function: Y = ( S S I E) ( S S I E) (S S I E) ( S S I E) = (m I E) (m I E) (m I E) (m I E) igital ircuits I -

4 Prof. r. J. Reichardt Prof. r.. Schwarz F Elektrotechnik/Informatik igital ircuits I -. ecoders (evice Selector) decoder is an n-input / n -output combinational device that activates one of the n outputs for each unique binary input pattern of m bits. Each output is identified by the minterm code m i of the binary input pattern it represents: decoder therefore is called a minterm code generator. ommercial decoders feature active low outputs and active low enable inputs. Function table: Enable Inputs Outputs G G G I I I Y Y Y Y Y Y Y Y Y i = S m i E i = n -

5 Prof. r. J. Reichardt Prof. r.. Schwarz F Elektrotechnik/Informatik to 8-bit decoder V code entity E_8 is port( I : in bit_vector( downto ); -- data input G, G_N, G_N : in bit; -- enable signals Y_N : out bit_vector( downto )); -- output lines end E_8; architecture E_8 of E_8 is signal EN: bit; -- local enable EN <= G and not G_N and not G_N; process(i, EN) variable TEMP: bit_vector( downto ); -- local test variable Y_N <= (others => ''); -- default assignment; aggregate TEMP := EN & I ; -- concatenation: vector & bit case TEMP is when "" => Y_N() <= ''; when "" => Y_N() <= '';... when "" => Y_N() <= ''; when others => null; -- no assignment end case; end process; end E_8; igital ircuits I -

6 Prof. r. J. Reichardt Prof. r.. Schwarz F Elektrotechnik/Informatik igital ircuits I -. emultiplexer emultiplexers are used as a controlled switch which assigns an input line to one out of n output lines. -to-8 decoder x8 can be used as a -to-8 demultiplexer (MU). The single data input I is connected to one of the active low enable inputs. The active low outputs and active low enable are of particular importance when a decoder is used as a MU because it is often paired with a MU for data routing. MU/MU system offers a time-shared bussing of multiple-line data Ii on a single line. ussing data over large distances by using this system results in savings on hardware, but is a relatively slow process. Inputs Outputs I Y Y Y Y Y Y Y Y

7 Prof. r. J. Reichardt Prof. r.. Schwarz F Elektrotechnik/Informatik igital ircuits I -. Encoder Encoders perform the inverse function of decoders. n encoder must generate a different output bit pattern for each input line that becomes active. If more than one input line is active the ouput depends on the priority of the input line. They convert n inputs to an n-bit code, where the n-bit code represents the highest priority input that is active (priority encoders). In addition, a commercial PE will usually have an enable-input and an enable-output ( EI, EO) that are used to cascade PEs. group signal output GS indicates a legitimate encoding condition. ata Inputs Outputs EI GS EO

8 Prof. r. J. Reichardt Prof. r.. Schwarz F Elektrotechnik/Informatik 8 to bit Priority encoder: V coding with if-then-else entity PEN_8 is port( _N : in bit_vector( downto ); -- priority inputs EI_N : in bit; -- enable low active _N : out bit_vector( downto ); -- binary output EO, GS_N: out bit); -- cascading outputs end PEN_8; architecture PEN8_ of PEN_8 is process(_n, EI_N) _N <= ""; GS_N <= ''; EO <= ''; -- default assignments if EI_N = '' then GS_N <= ''; if _N() = '' then _N <= ""; -- inverted elsif _N() = '' then _N <= ""; elsif _N() = '' then _N <= "";... elsif _N() = '' then _N <= "";"; -- inverted else _N <= ""; GS_N <= ''; EO <= ''; ";-- no _N input active end if; end if; end process; end PEN8_; igital ircuits I -8

9 Prof. r. J. Reichardt Prof. r.. Schwarz F Elektrotechnik/Informatik. ode onverters Frequently it is necessary to convert one code to another. code converter is a device that associates to each agreed pattern of n-inputs a corresponding m-output combination. n example to illustrate the code converter design process is given with the Gray-to-binary conversion for -bit codes. In order to apply K-maps for minimising the logic, the correct minterm code of all input patterns has to be considered. No. m i G G G G G G G G G G G G G G G G G G G G G G G G igital ircuits I -9

10 Prof. r. J. Reichardt Prof. r.. Schwarz F Elektrotechnik/Informatik -to-seven-segment display (I) ight-emitting diodes (Es) and liquid crystal displays (s) are used to produce the arabic numerals. For each decimal digit several segments (S...S) have to be controlled. The truth table describes a -input/-output code converter. The last six input patterns will not occur because we expect -inputs, therefore don t-care entries can be made to reduce the logic. If false data rejection (FR) is necessary the code converter should yield one single letter, i. e. E for all input patterns which do not belong to the code word set. ec S S S S S S S S S S S S S S igital ircuits I -

11 Prof. r. J. Reichardt Prof. r.. Schwarz F Elektrotechnik/Informatik igital ircuits I - -to-seven-segment display (II)

12 Prof. r. J. Reichardt Prof. r.. Schwarz F Elektrotechnik/Informatik -Segment code converter V description ab application with the S9-oard -- SEG.vhd -- Seven Segment ode onverter for S-9 emoboard S/P S/P S/P S/P --S/P9 S/P S/P entity SEG is port(input: in bit_vector( downto ); --Pins,,, SEGMENTS: out bit_vector( downto )); end SEG; igital ircuits I -

13 Prof. r. J. Reichardt Prof. r.. Schwarz F Elektrotechnik/Informatik architecture ONVERTER of SEG is EOER: process( INPUT) case INPUT is --"S S S S S S S" when "" => SEGMENTS <= ""; when ""=> SEGMENTS <= ""; when ""=> SEGMENTS <= ""; when ""=> SEGMENTS <= ""; when ""=> SEGMENTS <= ""; when ""=> SEGMENTS <= ""; when ""=> SEGMENTS <= ""; when ""=> SEGMENTS <= ""; when ""=> SEGMENTS <= ""; when ""=> SEGMENTS <= ""; -- when ""=> SEGMENTS <= "";-- -- when ""=> SEGMENTS <= "";-- b -- when ""=> SEGMENTS <= "";-- c -- when ""=> SEGMENTS <= "";-- d -- when ""=> SEGMENTS <= "";-- E -- when ""=> SEGMENTS <= "";-- F when others => SEGMENTS <= "";-- Error end case; end process EOER; end ONVERTER; igital ircuits I -

14 Prof. r. J. Reichardt Prof. r.. Schwarz F Elektrotechnik/Informatik Survey of combinational components Type Input-/Output- ines Multiplexer ata: n fi Select: n ecoder Select: n fi n Enable: 晦 typically emultiplexer ata: fi n Select: n Priority Encoder Select: n fi n ommercial ircuits x: Single 8-ine to -ine MU x: ual -ine to -ine MU x: Quadruple -ine to -ine MU x8: Single -ine to 8-ine IN/OT x9: ual -ine to -ine /Y Types as above. single data input is connected to one enable line. x8: Single 8-ine to -ine PRI/IN Not available in advanced high-speed MOS technology (). ode onverter ata: k fi l x8: Single -ine to 8-ine IN/OT inary code to one out of eight code. pplication ata Selectors/Switches. One out of n input data lines is connected to the output. Switches multiple sources to a data bus or other devices. n-it binary input pattern activates one out of n output lines: Memory selection/enable in a microprocessor-system. n-it select lines perform a input data routing to n output lines. n active input line with the highest priority generates a corresponding binary output pattern. Prioritised peripheral interfaces request communication to a microprocessor system. ssignment of l output line to k input lines according to a problem specific coding. igital ircuits I -

15 Prof. r. J. Reichardt Prof. r.. Schwarz F Elektrotechnik/Informatik. 8-bit Magnitude omparator -- 8-bit comparator 8 entity KOMP8 is port(, : in bit_vector( downto ); T_N, EQ_N, GT_N : out bit); end KOMP8; architecture OMP8_ of KOMP8 is signal TEMP: bit_vector( downto ); -- local signal to avoid buffer mode process(, ) TEMP <= ""; -- default assignment if > then TEMP() <= ''; elsif = then TEMP() <= ''; end if; -- else is substituted by default end process; (EQ_N, GT_N) <= TEMP; -- aggregate as target T_N <= TEMP() nand TEMP(); -- concurrent end OMP8_; igital ircuits I -