Calcolatori Elettronici Anno Accademico 2001/2002. FSM in VHDL. Macchina a Stati Finiti (FSM) Tipo Moore. Esempio: Macchina di Moore a due stati

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1 Macchina a Stati Finiti (FSM) Tipo Moore Calcolatori Elettronici Anno Accademico 2/22 FSM in VHDL Gianluca Palermo Politecnico di Milano Dipartimento di Elettronica e Informazione gpalermo@fusberta.elet.polimi.it IN NEXT NEXT 2 CURRENT Esempio: Macchina di Moore a due stati S/ S/ OUTPUT OUT Esempio: Macchina di Moore (3 process) entity moore is port( clk,rst,input: in bit; output:out bit); end moore; architecture ex of moore is type state_type is (S,S); signal current_state, next_state: state_type; ff: process (clk,rst) if rst = then state <= S; elsif (clk'event and clk = '') then current_state <= next_state; end process ff; st: process (current_state) when S => if input= then next_state <= S; next_state <= S; Esempio: Macchina di Moore (3 process) when S => if input= then next_state <= S; next_state <= S; end process st; out_p: process (current_state) when S => output <= ; when S => output <= ; end process out_p; end ex; 3 4

2 Esempio: Macchina di Moore (2 process) entity moore is port( clk, rst, input: in bit; output: out bit); end moore; architecture ex2 of moore is type state_type is (S,S); signal current_state, next_state: state_type; ff: process (clk,rst) if rst = then state <= S; elsif (clk'event and clk = '') then current_state <= next_state; end process ff; st: process (current_state, input) when S => output <= ; if input= then next_state <= S; next_state <= S; 5 Esempio: Macchina di Moore (2 process) when S => output <= ; if input= then next_state <= S; next_state <= S; end process st; end ex2; 6 Esempio: FSM_ Tipo Moore Codice Sorgente di FSM_ Tipo Moore C_IN [ ] FSM_ Y_OUT [ ] ST ST ST,- - -,- ST Y_OUT,- entity FSM_ is port (, : in bit; C_IN : in bit_vector ( to ); Y_OUT : out bit_vector ( to )); end FSM2; architecture MOORE of FSM_ is type _TYPE is ( ST,,, ); Processo sequenziale SEQ: process (, ) if = '' then CURRENT_ <= ST; elsif ('event and = '') then 7 8

3 Codice Sorgente di FSM_ - Tipo Moore (cont.) Processo Combinatorio per Next State Logic COMB: process (current_state,c_in) when ST => if (C_IN="" or C_IN="" or C_IN="") then NEXT_ <= ; NEXT_ <= ST; when => if (C_IN="" or C_IN="" or C_IN="") then NEXT_ <= ; NEXT_ <= ST; when => if (C_IN="" or C_IN="" or C_IN="") then NEXT_ <= ; NEXT_ <= ; 9 Codice Sorgente di FSM_ - Tipo Moore (cont.) when => if ( C_IN="" or C_IN="") then NEXT_ <= ; NEXT_ <= ; end process COMB; Processo Combinatorio per Output Logic OUT_: process (CURRENT_) when ST => Y_OUT <= ""; when => Y_OUT <= ""; when => Y_OUT <= ""; when => Y_OUT <= ""; end process OUT_; end MOORE; Esempio: FSM_A Tipo Moore Codice Sorgente di FSM_A Tipo Moore X FSM_A S S X = S S S S X = S entity FSM_A is port( X, : in bit; : out bit); end FSM_A; architecture MOORE of FSM_A is type _TYPE is ( S, S,, ); SEQ: process wait until('event and = ''); COMB_OUT:process (CURRENT_, X) when S => <= ; if (X = ) then NEXT_ <= S; NEXT_ <= ; 2

4 Codice Sorgente di FSM_A Tipo Moore (cont.) when S => <= ; if (X = ) then NEXT_ <= S; NEXT_ <= ; when => <= ; if (X = ) then NEXT_ <= ; NEXT_ <= ; when => <= ; if (X = ) then NEXT_ <= ; NEXT_ <= S; end process COMB_OUT; end MOORE; Macchina a Stati Finiti (FSM) Tipo Mealy IN CURRENT_ NEXT and OUTPUT NEXT_ OUT 3 4 Esempio: FSM_B Tipo Mealy Codice Sorgente di FSM_B Tipo Mealy X STA STB STC STD / X = STB / STB / STC / STD / 5 STA / STB X = STC / STD / STD / STA / / / / STC / STD / / entity FSM_B is port ( X, : in bit; : out bit); end FSM_B; architecture MEALY of FSM_B is type _TYPE is ( STA, STB, STC, STD); SEQ: process wait until('event and = ''); COMB_OUT:process (CURRENT_, X) when STA => if (X = ) then <= ; NEXT_ <= STB; <= ; NEXT_ <= STC; 6

5 Codice Sorgente di FSM_B Tipo Mealy (cont.) when STB => if (X = ) then <= ; NEXT_ <= STB; <= ; NEXT_ <= STD; when STC => if (X = ) then <= ; NEXT_ <= STC; <= ; NEXT_ <= STD; when STD => if (X = ) then <= ; NEXT_ <= STD; <= ; NEXT_ <= STA; end process COMB_OUT; end MEALY; 7

2011 Dr. Vassiliy Tchoumatchenko. Въведение в VHDL Проектиране на Крайни Автомати с VHDL

2011 Dr. Vassiliy Tchoumatchenko Въведение в VHDL Проектиране на Крайни Автомати с VHDL Диаграма на Състоянията на Краен Автомат Reset B = 1 2 State 0 X