10-bit Pipeline ADC Design

Transcription

1 Wenxu Zhao ID: ECE592 Analog Digital Converter 10-bit Pipeline ADC Design Part I Results 1. Block diagram A 10-bit pipeline ADC was designed with 100MHz nyquist frequency at full scale of 500mV. A 1.5-bit sub-adc was implemented in each stage. Delay & Combine CLK ф1 D Q CLK ф1 Σ D Q CLK Σ D Q CLK 10 Dout Vin SHA Stage 1 Stage 2 Stage 10 ф1 ф1 ф1 Vin1 SHA Σ G Vres1 ADC DAC - 2 Unit Stage Figure 1 Diagram of 10 bit pipeline ADC implemented with 1.5 bit sub ADC 2. Nonlinearity performance Table 1 DNL/INL and ENOB calculated from Monte Carlo Simulation Offset Noise Gain error DNL (3σ) INL (3σ) ENOB (no cali) ENOB (with cali) σ = 3mV σ = 1mV σ = lsb 39 lsb 4.7 bits 8 bits 3. Timing domain and FFT analysis SNDR =63.34dB ENOB=10.2 bits Figure 2 Testbench configuration for time domain and FFT analysis 4. Limiting factors of ENOB The nonlinearity of gain block in the first several stages contributes to the DNL/INL degradation. For instance, 1 σ (3mV) of input offset in the gain block of first stage would result in a DNL of 6.15 lsb (lsb = 0.488uV) at the output.

2 Part II Simulation and Calculation Figure 3 DNL of each code without calibration Figure 4 INL of each code without calibration σ_(dnl_max) = 2.4 lsb σ_(inl_max) = 13 lsb Figure 5 SNDR of a 101MHz sine wave input Table 2 FFT analysis of sine wave input f f f B N SNDR ENOB 101MHz 1GHz 10GHz dB 10.2 bits ENOB = (SNDR-1.76)/6.02 = 10.2 bits

3 Part III Calibration of gain stage input offset An ideal 5-bit DAC driven by finite state machine was designed to implement the offset calibration scheme. The full scale of 5-bit DAC is from -10mV to 10mV, successfully covers the 3σ (9mV) offset mismatch of gain input. IDLE Startup FIRST MAX offset? NO Ideal DAC 5 FSM YES INCREASE NO Vin + + Σ G Vout MIN offset? YES KEEP Figure 6 Block diagram of calibration method Figure 7 Flow diagram of calibration (FSM) Two worst case of offset scenarios (± 3 σ) demonstrations: Gain input Gain output Figure 8 start up calibration for 9mV input offset Note 9mV offset has been cancelled by DAC output of 8.75mV, resulting in an overall 250uV input offset Gain input Gain output Figure 9 start up calibration for 9mV input offset Note 9mV offset has been cancelled by DAC output of 8.75mV, resulting in an overall 250uV input offset

4 Appix A. Finite state machine implemented with Verilog-a code // VerilogA for pipeline_adc, offset_cali_fsm, veriloga // case should be put into clock block `include "constants.vams" `include "disciplines.vams" `define IDLE 0 `define FIRST 1 `define INCREASE 2 `define KEEP 3 module offset_cali_fsm (clk, gain, dac, finish); input clk, gain; electrical clk, gain; output [4:0] dac; output finish; electrical [4:0] dac; electrical finish; parameter real zero = 0; parameter real one = 2; parameter real vth = 1; parameter real slack = 1p from [0:inf); parameter real trise = 10p from [0:inf); parameter real tfall = 10p from [0:inf); parameter real tconv = 10p from [0:inf); parameter integer traceflag = 0; integer counter, counter_current, offset, offset_current, ii; integer current_state, next_state; real gain_p2, gain_p1, gain_current; real dac_out[4:0]; real finish_out; analog begin

5 @( initial_step or initial_step("dc", "ac", "tran", "xf") ) begin counter = zero; counter_current = zero; offset = zero; current_state = `IDLE; next_state = `IDLE; gain_p2 = zero; gain_p1 = zero; gain_current = zero; finish_out = zero; generate i (4, 0) begin dac_out[i] = cross (V(clk)-vth, 1, slack ) ) begin // counter = counter+1; counter_current = counter; gain_p2 = gain_p1; gain_p1 = gain_current; current_state = next_state; case (current_state) `IDLE: begin next_state = `FIRST; finish_out = zero; generate i (4, 0) begin dac_out[i] = zero; gain_current = V(gain); `FIRST: begin // next_state = SECOND; finish_out = zero; generate i (4, 1) begin dac_out[i] = zero;

6 dac_out[0] = one; gain_current = V(gain); if ( abs(gain_p1) < abs(gain_current) ) begin next_state = `KEEP; else begin next_state = `INCREASE; `INCREASE:begin finish_out = zero; for (ii = 0; ii<=4; ii = ii+1) begin if(counter_current%2) begin dac_out[ii] = one; else begin dac_out[ii] = zero; counter_current = counter_current/2; gain_current = V(gain); if ( abs(gain_p1) < abs(gain_current) && abs(gain_p1) < abs(gain_p2) ) begin next_state = `KEEP; else begin next_state = `INCREASE; offset = counter-1; `KEEP: begin finish_out = one; offset_current = offset; for (ii = 0; ii<=4; ii = ii+1) begin if(offset_current%2) begin dac_out[ii] = one; else begin dac_out[ii] = zero; offset_current = offset_current/2; next_state = `KEEP;

7 case V(finish) <+ transition (finish_out, tconv, trise, tfall); generate i (4, 0) begin V(dac[i]) <+ transition ( dac_out[i], tconv, trise, tfall ); module

8 B. Matlab code for FFT analysis % Code for FFT analysis of Pipeline ADC followed by ideal DAC output % Author: Wenxu Zhao % Date: 11/12/2013 % Input frequency = MHz % ADC clock = 1GHz % Fs = 10GHz clear all close all fc = 5e8; %cutoff frequency for SNDR calculation fadc = 1e9; fs = 1e10; N = 8192; cycles = 83; fx = ; % fx=fs*cycles/n B = 10; Vfs = 0.5; LSB = Vfs/(2^B-1); %take FFT data = load('101m_1g_10g_8192.matlab'); y = data (:,2); % second column of data length_data = length(y); y=y.'; Y = abs(fft(y, N)); Y = Y(1:/2)./N*2; PSD = fft(y, N).*conj(fft(y, N))./N./fs; psd_db = 10*log10(PSD); figure(1) plot(fx/fs.*[0:n-1],psd_db); title('psd') xlabel('bins') ylabel('psd') % frequency vector f = [0:N/2-1]/N;

9 figure(2) plot(f, 20*log10(Y(1:N/2)),'-b'); title('fft') xlabel('frequency [f/fs]') ylabel('dft Magnitude [dbfs]') % calculate SNR Boser_quantization_noise_2 sigbin = find(y==max(y)); %find signal bin r = Y(sigbin+1:); %find image bin image_bin = find(y==max(y)); %store image bin noise = [Y(2:sigbin-1), Y(sigbin+1:round(N*fadc/fs/2))]; %only count upto fdac/fs; sndr = 10*log10( Y(sigbin)^2/sum(noise.^2) ); quant_noise=10*log10((sum(noise.^2))); quant_noise_calc=10*log10((lsb^2/b)); sig_power=(y(sigbin)^2); enob = (sndr )/6.02; figure(3); [enob,sndr,sfdr,snr] = prettyfft(y, fs); SNDR = sndr; ENOB = (sndr-1.76)/6.02;

10 C. Matlab code for DNL/INL calculation clear all; close all; N_mc = 49; N_code = 1024; OSR = 10; dac_data = load('dac_49_sampled.matlab'); %dac_out = []; %1D dnl = []; %2D DNL results inl = []; for n = 1:N_mc dac_out = dac_data(:, n*2); length_code = length(dac_out); Wavg = length_code/n_code; counter_dnl = 1; code_dnl = 1; for m = 2:length_code code_previous = dac_out(m-1); code_current = dac_out(m); if code_previous == code_current counter_dnl = counter_dnl + 1; else dnl(code_dnl, n) = (counter_dnl-wavg)/wavg; if code_dnl < 2 inl(code_dnl, n) = 0; else inl(code_dnl, n) = inl(code_dnl-1, n) + dnl(code_dnl, n); code_dnl = code_dnl + 1; counter_dnl = 1; dnl_rms = []; N_dnl_rows = size(dnl,1); for k = 1:N_dnl_rows dnl_rms(k) = sqrt(mean(dnl(k).^2));

11 figure(1) plot(dnl_rms); title('monte Carlo DNL'); ylabel('dnl(rms)'); xlabel('codes'); inl_rms = []; N_inl_rows = size(inl,1); for l = 1:N_inl_rows inl_rms(l) = sqrt(mean(inl(l).^2)); figure(2) plot(inl_rms); title('monte Carlo INL'); ylabel('inl(rms)'); xlabel('codes');