Sequential Gates. Gate Level Design. Young Won Lim 3/15/16

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1 equential Gates Gate Level esign

2 Copyright (c) Young W. Lim. Permission is granted to copy, distribute and/or modify this document under the terms of the GNU Free ocumentation License, Version 1.2 or any later version published by the Free oftware Foundation; with no Invariant ections, no Front-Cover Texts, and no Back-Cover Texts. A copy of the license is included in the section entitled "GNU Free ocumentation License". Please send corrections (or suggestions) to youngwlim@hotmail.com. This document was produced by using OpenOffice and Octave.

3 NO-based Latch ET T ET T ET =1 =0 EET =0 =1 HOL =old Hold Hold Hold Hold =old equential Gates (3B) 3

4 NO-based Latch tates HOL EET ET NO based Latch ET =1 =0 =0 =1 =1 =0 EET =0 =1 HOL =old =old equential Gates (3B) 4

5 NAN-based Latch ET T ET T ET =1 =0 EET =0 =1 Hold Hold Hold Hold HOL =old =old equential Gates (3B) 5

6 NAN-based Latch tates HOL EET ET NAN based Latch ET =1 =0 =0 =1 =1 =0 EET =0 =1 HOL =old =old equential Gates (3B) 6

7 Latch ymbols HOL EET ET NO based Latch HOL EET ET NAN based Latch equential Gates (3B) 7

8 Active High and Low Inputs Active High Active High Active High Active Low Active Low Active Low equential Gates (3B) 8

9 NO-based Latch ET T ET T C C transparent opaque transparent opaque Hold Hold equential Gates (3B) 9

10 NO-based Latch HOL EET ET NO based Latch C C C=0 =X C=1 =0 C=1 =1 C=0 =X C=1 =1 =0 =1 C=1 =0 =1 =0 equential Gates (3B) 10

11 Master-lave FlipFlop Master Latch Y Y lave Latch Y Master-lave F/F the hold output of the master is transparently reaches the output of the slave this value is held for another half period equential Gates (3B) 11

12 Master-lave FlipFlop Falling Edge Master Latch Y C C Y lave Latch equential Gates (3B) 12

13 Master-lave FlipFlop ising Edge Master Latch Y C C Y lave Latch equential Gates (3B) 13

14 Latch & FlipFlop Level ensitive Latch =1 transparent =0 opaque C Edge ensitive FlipFlop =1 0 transparent else opaque equential Gates (3B) 14

15 FlipFlop with Enable EN EN 0 1 EN EN equential Gates (3B) 15

16 Advantages of Latches over FFs Flipflop designs are very easy to verify timing Each path between flip-flops must be less than the clock period Tools check for skew, setup, and hold time violations hort paths are padded (buffers are added to slow down the signals) kew in flip-flop based systems affects the critical path Most designs in industry are based on flip-flops Latch designs are more flexible than a flip-flop design Need to CA tools to make sure it works Can borrow time to allow a path to be longer than clock period Can tolerate clock skew -- skew does not directly add to cycle time Less silicon area equential Gates (3B) 16

17 Latches at the output ports TI Latch W TI C ATA Latch data bus W port C equential Gates (3B) 17

18 Classical Edge Triggered FF i1 o1 CLK i3 i2 o2 o3 Output tage Latch Input tage Latches =0/1 i4 o4 i1 o1 CLK i2 o2 CLK i3 o3 * figures from wikipedia.org i4 o4 equential Gates (3B) 18

19 Classical Edge Triggered FF CLK=0 HOL op for the ouput latch CLK=1 ET, EET op for the ouput latch Output tage Latch =1 =0 equential Gates (3B) 19

20 Classical Edge Triggered FF reset hold set hold set hold reset hold set hold set equential Gates (3B) 20

21 Classical Edge Triggered FF CLK=0 HOL op for the ouput latch CLK=1 ET, EET op for the ouput latch Output tage Latch CLK=0 1 When =0 HOL EET When =1 HOL ET CLK=1 0 EET HOL ET HOL equential Gates (3B) 21

22 Output Latch Operation (Classical Edge Triggered FF) CLK=0 HOL op for the ouput latch CLK=1 ET, EET op for the ouput latch Output tage Latch CLK=0 1 When =0 HOL EET When =1 HOL ET CLK=1 0 EET HOL ET HOL equential Gates (3B) 22

23 equential Element Types CMO Latches CMO FlipFlops Pulsed Latches Latches and FlipFlops with a eset Latches and FlipFlops with an Enable equential Gates (3B) 23

24 eferences [1] [2] [3] W. Wolf, Modern VLI esign : ystems on ilicon [4] N. Weste,. Harris, CMO VLI esign: A Circuits and ystems Perspective [5] J. P. Uyemura, Introduction to VLI Circuits and ystems [6] [7] [8] [9] [10]

Lecture 20: Sequential Circuits. Sequencing

Lecture 20: Sequential Circuits Sequencing Elements Simple /FF Timing efinitions Source: Ch 7 (W&H) Sequencing Use flip-flops to delay fast tokens so they move through exactly one stage each cycle. Inevitably