Eliminating the Error Floor for LDPC with NAND Flash

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1 Eliminating the Error Floor for LDPC with NAND Flash Shafa Dahandeh, Guangming Lu, Chris Gollnick NGD Systems Aug

2 Agenda 3D TLC & QLC NAND Error Characteristics Program/Erase Cycling (Endurance) Data Retention Read Disturb LDPC Error Floor Performance LDPC Overview Normalized Min-Sum Decoder Performance NGD Systems Decoder Performance

3 Characterization Platform FPGA Platforms Multiple Dies / Channels Multiple Blocks Pseudo-random pattern P/E Cycling Stress Data Retention Read Disturb Raw BER (RBER) measured at multiple threshold voltage (V th ) levels NAND Module Controller NAND Test Module 3

4 P/E Cycling Test Procedure Erase multiple blocks to EOL and beyond Program block 3 pages per WL (TLC) pages per WL (QLC) Starting with the first cycle, perform a read operation at n th interval of P/E cycles and measure RBER

18 Average RBER Capacity (bits/cell) P/E Cycles (TLC) Average RBER

had ~5X step increase in RBER X increase in RBER at EOL 1% capacity

16 1 1 1 8 6 RBER 1 1 1 8 6.98.978.976.97.97.97...6.8 1 1.

5 18 Average RBER Capacity (bits/cell) P/E Cycles (TLC) Average RBER excluding marginal BLK over different Vth 16 Mid P/E, one block had ~5X step increase in RBER X increase in RBER at EOL 1% capacity loss Excluding marginal block No shift in optimum threshold voltage RBER PE Cycle TLC Capacity PE Cycle -3 Vth PE 5

Average RBER Capacity (bits/cell) RBER P/E Cycles (QLC) 15 Average RBER over PE @

TLC No shift in optimum threshold voltage 1 1 1 8 6 1 3.9 3.9 3.88 3.

6 Average RBER Capacity (bits/cell) RBER P/E Cycles (QLC) 15 Average RBER over different Vth RBER linearly increased at EOL 5% capacity loss RBER bathtubs narrower than TLC No shift in optimum threshold voltage PE Cycle (xeol) QLC Capacity PE (xeol) PE Cycle (xeol) -1 - Vth 6

Retention (Year) Data Retention Test Procedure JESD18 specifies Client and Enterprise Data Retention at 1 year, 3 C and 3 months, C, respectively Arrhenius equation was used to test the 3D NAND

7 Retention (Year) Data Retention Test Procedure JESD18 specifies Client and Enterprise Data Retention at 1 year, 3 C and 3 months, C, respectively Arrhenius equation was used to test the 3D NAND devices under accelerated environment for short period of time to emulate the JESD18 spec Client Retention (Power Off) Enterprise Retention (Power Off) Ambient temp (C) 7

8 RBER Capacity (bits/cell) EOL Data Retention (TLC) 5 Average different Vth X increase in RBER at EOL DR % capacity loss w/o V th optimization 1X increase in RBER at EOL DR RBER % capacity loss w/ V th optimization Data Retention 3 TLC Capacity Optimum Vth pre DR Optimum Vth post DR 15 DR 3 mons, C DR 3 hrs, RT DR 3 mons, C Data Retention DR 3 hrs, RT Vth Data Retention 8

9 RBER RBER Capacity (bits/cell) EOL Data Retention (QLC) X RBER increase at EOL DR Without threshold optimization 1% capacity loss X increase in RBER at EOL DR With threshold optimization 3% capacity loss Average different Vth Data Retention QLC Capacity Optimum Vth pre DR 5 Optimum Vth post DR DR 3 mons, C DR 3 hrs, RT DR 3 mons, C DR 3 hrs, RT Data Retention 9 Data Retention - -1 Vth

10 Read Disturb Test Procedure Both WordLines and BitLines were tested for Read Disturb WL 1 was read up to K cycles on multiple blocks for WordLine disturb Every 1K cycles, RBER was measured on 1 WLs with relative locations +/-1, 5, 1,, and to WL 1 Start RD cycle 1: Read WL 1 on multiple Blocks RD cycle 1 RD cycle 1K RD Cycle K Select 1 WLs with relative locations +/-1, 5, 1,, and to WL 1 on every 1K Reads Measure RBER at different V th levels 1

11 EOL Read Disturb (TLC) 8 Bitline Read Disturb 7 RBER Capacity (bits/cell) BAR plot shows RBER on 1 WLs with relative locations +/-1, 5, 1,, and to WL 1 RBER increased -3 times 1% capacity loss No shift in optimum V th RBER Ratio Average different Vth Read Disturb Count 1 WL position TLC Capacity Read Disturb Count 1 11

12 EOL Read Disturb (QLC) 3.5 Bitline Read Disturb RBER on WLs with relative locations +/-1 to WL 1 RBER increased -3 times Affected WL and BL 5% capacity loss RBER Ratio RBER Capacity (bits/cell) WL position Average different Vth TLC Capacity Shift in optimum V th observed Read Disturb Count Read Disturb Count 1 1

13 EOL Program/Erase increased RBER by factor of on average RBER increase follows a linear relation to PE cycling 1% - 5% capacity loss Data Retention was seen to have the most impact to RBER and a significant shift in the optimum V th EOL DR increased RBER by factor of 1 with optimized V th % capacity loss w/o V th optimization Read Disturbance increases RBER EOL RD increased RBER -3 times 1% - 5% capacity loss 3D TLC/QLC Key Findings 13

14 LDPC Performance LDPC Performance LDPC Overview Normalized Min-Sum Decoder Performance NGD Systems Decoder Performance 1

15 Program/Erase cycles increase RBER linearly (X) Up to 5% loss in capacity Data Retention has the highest impact on RBER (1X X) Up to % loss in capacity Read Disturb increases RBER (X 3X) Up to 5% loss in capacity 3D NAND Error Characteristics Multi-Code-Rate LDPC, media management and signal processing are required to mitigate the RBER increase due to various stress factors and extend the NAND lifetime, but Not all LDPC codes perform the same Extreme care must be taken in the design to have good waterfalls while avoiding error floors 15

16 Uncorrectable Bit Error Rate (UBER) LDPC Overview LDPC codes have emerged as top candidates for capacity approaching error correction in many data storage systems One class of LDPC codes that allows lowcomplexity is quasi-cyclic (QC-LDPC) codes QC- LDPC codes are not guaranteed to perform well Depending on the design, error-correction performance only observed until moderate BER At lower BER, the error curve often changes its slope (error floor) LDPC Waterfall and Error Floor Waterfall Error Floor Raw Bit Error Rate (RBER)) Improving Raw Bit Error Rate 16

17 LDPC Decoders Standard belief-propagation (BP), or sum product algorithm (SPA) can achieve good performance, but Hardware implementation too costly Min-Sum (MS) algorithm, achieves good tradeoff between complexity and error performance. MS algorithm, however has performance loss due to overestimation at check nodes Decoding performance can be improved by employing normalization scaling (Normalized Min-Sum, NMS) m old VAR-to-CHK operation LLR out LLR in MUX Message (m) Memory Q new APP Memory Q Memory CHK-to-VAR operation LLR out Source: Check node operation m new 17

18 Uncorrectable Bit Error Rate (UBER) NMS Decoder Performance 18 Multiple H matrices were used to test NMS decoder for error floors Modeling 1 and FPGA were used to estimate error floor Error floors were measured with optimized H matrices All codes showed error floor in the 1^-1 to 1^-13 UBER region Error floor regions much higher than required for SSD Raw Bit Error Rate 1. Acknowledgements to Dr. Amir Banihashemi, and Ali Farsiabi from Carleton University for collaborations on error floor analysis HD-NMS Performance Code 1, NMS, Model Code, NMS, Model Code 3, NMS, Model Code, NMS, Model Code 5, NMS, Model Code 1, NMS, FPGA Code, NMS, FPGA Code 3, NMS, FPGA Code, NMS, FPGA Code 5, NMS, FPGA

19 Uncorrectable Bit Error Rate (UBER) NGD Systems Decoder Performance NGD Systems uses proprietary features to eliminate error floors Not post processing Operates on-the-fly No latency impact Same optimized H matrices were used to test NGD Systems decoder for error floors All error floors eliminated Improves SSD reliability significantly NGD Systems HD Performance Code 1, NMS, Model Code, NMS, Model Code 3, NMS, Model Code, NMS, Model Code 5, NMS, Model Code 1, NMS, FPGA Code, NMS, FPGA Code 3, NMS, FPGA Code, NMS, FPGA Code 5, NMS, FPGA Code 1, NGD Systems Code, NGD Systems Code 3, NGD Systems Code, NGD Systems Code 5, NGD Systems Raw Bit Error Rate 19

20 UBER UBER LDPC Performance vs. 3D TLC/QLC RBER TLC 1-6 QLC EOL PE Avg. RBER 1-1 BOL RD Avg. RBER 1 Marginal -1 Block Use Multi-Read, RAID EOL DR Avg. RBER BOL DR Avg. RBER 1-1 EOL PE/DR/RD Avg. RBER BOL Avg. RBER BOL Avg. RBER RBER RBER

21 Thank You! Questions? Visit NGD Systems Booth #618 NGD Systems Next-Generation Newport Platform for Computational Storage 1

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