ECE 410 Homework 1 -Solutions Spring 2008

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1 ECE 410 Homework 1 -Solution Spring 2008 Prolem 1 For prolem 2-4 elow, ind the voltge required to keep the trnitor on ppling the rule dicued in cl. Aume VDD = 2.2V FET tpe Vt (V) Vg (V) Vi (V) n-tpe n-tpe c p-tpe d p-tpe e p-tpe Vg Vo Vi ) Vg-Vi = = 1.2 > Vtn, o Vo = Vi = 1V ) Vg-Vi = = 0.5 < Vtn= 0.6, o Vo = Vg-Vtn = = 0.9V c) Vi-Vg = 2 0 = 2 > Vtp, o Vo = Vi = 2V d) Vi-Vg = = 0.3 < Vtp, o Vo = Vg+ Vtp = = 2.2V e) Vi-Vg = = 0.5 = Vtp, o Vo = Vi = 1.5V or Vo = Vg+ Vtp = = 1.5V which prove tht in the equl ce, either work nd give the me nwer Prolem 2 Find the midpoint voltge, V, nd put voltge, Vo, or the chin o two nfet p trnitor hown elow or the ollowing ce. Aume VDD = 2.5V nd Vtn = 0.5V. () Vi = 0V VDD VDD Here VDD-Vi = 2.5 > Vtn, o V = Vi = 0V Vi Vo nd VDD-V = 2.5 > Vtn, o Vo = V = 0V V notice thi i how tht two erie nmos cn pull the put to ground when the Vi node i t ground ( in NAND gte). () Vi = 1.1V Here VDD-Vi = 1.4 > Vtn, o V = Vi = 1.1V nd VDD-V = 1.4 > Vtn, o Vo = V = 1.1V (c) Vi = 2.2V Here VDD-Vi = 0.3 < Vtn, o V = VDD-Vtn = 2.0V nd VDD-V = 0.5 = Vtn, o Vo = V = 2V Notice when Vg-Vi = Vtn ou get the me nwer i ou ue ce 1 or ce 2, or emple, in thi prolem ce 2 give Vo = VDD Vtn = 2V, which i the me ce 1. Homework 1 Solution p. 1

2 Prolem 3 Uing undmentl logic propertie, prove the ollowing logic reltionhip () (+)(+c) = +c Firt epnd the term (ue the FOIL method o mthemtic) (+)(+c) = + + c + c = + + c + c (ince = ) = (1+) + c + c = + c + c (ince 1+ = 1 nd 1 = ) = (1+c) + c = + c (ince 1+c = 1 nd 1 = ) () + ' = + Firt the e w. Since we know rom prt () ove tht + = (+)(+) let =, =, nd = thu + = (+ )(+) = + (ince + = 1) Or, i we tick with the undmentl propertie we cn ollow the tep in prt () in revere + = (1+ ) + = + + = (1+) + + = = (+ )(+) = + (ecue + = 1 nd 1(+) = + Prolem 4 Deign CMOS logic gte or the unction = + ( + ) uing the let numer o trnitor completing the ollowing tep: ) Identi the nmos portion o the circuit etting up nd reducing the eqution or n nd then implementing thi eqution gte-level chemtic. Note, ecue thi i nmos logic, the gte-level chemtic hould hve n inverion t the put ut no inverion t the input (ert-high logic). ) Appl ule puhing on the gte-level chemtic in () to contruct the gte-level chemtic or the pmos portion o the circuit. Here, the ule t the put mut e puhed to the input nd ll input mut hve ule on them (ert-low logic). Be ure to properl ppl the DeMorgn reltion nd modi logic gte ppropritel. c) Ue the gte-level chemtic in () to contruct the trnitor-level chemtic or the nmos portion o the circuit, properl ppling the erie/prllel trnitor rule or ech AND nd OR unction. d) Repet prt (c) or the pmos portion o the circuit, dding thi to the top o the nmos portion to orm complete CMOS logic circuit. Homework 1 Solution p. 2

3 ) Firt, etup the nmos eqution nd reduce it. Fn = = +(+) = + + = (+1) + = + which cn e implemented in logic gte hown in Fig. A where the ule t the put repreent the inverting nmos logic. ) Net, ue thi logic gte chemtic nd puh the ule t the put to the input in order to implement the pmos network. See Fig. B. c, d) Finll, ue AND = erie nd OR = prllel to implement oth network with trnitor, hown in Fig. C. (A) (B) Prolem 5 (C) Follow the procedure elow to contruct the CMOS logic gte or the unction = + c. ) Write the eqution or the nmos network. ) Write the eqution or the pmos network. c) Ue the eqution in () nd () to contruct chemtic or. d) Veri the nmos nd pmos network re proper complement (erie group in nmos re prllel in pmos, etc.). Homework 1 Solution p. 3

4 ) Since the entire unction i inverted, we jut remove the top-level inverion to orm n. n = ( c) + But we till need to remove the inverted opertion n = ( c) + = +c + ) Firt, remove ll inverted opertion. Below the mol repreent NOT = (( c) +) = ( c) Now invert ll o the input to orm p p = c Notice tht now p nd n oth hve the me input (,, ) nd the opertion in p (ll AND) re complement o the opertion in n (ll OR). c) c c d) Oervtion o the chemtic how tht the pmos nd nmos network hve the me input ignl (, c, ) nd ech o the opertion i complemented within the other network, i.e., ll erie comintion in pmos re prllel comintion in nmos. Homework 1 Solution p. 4

5 Prolem 6 (Deign Chllenge) ) A dicued in lecture, the XOR nd XNOR CMOS chemtic re ver imilr; the hve ectl the me tructure ut two o the input re dierent. Bed on thi, contruct gtelevel chemtic (no trnitor, jut gte mol) or circuit tht ue onl one XOR gte to implement oth XOR nd XNOR unction. The mol or the CMOS XOR gte i hown elow, hving input, (NOT ),, nd (NOT ). A ignl S hould e ued to elect etween the XOR nd XNOR unction. You cn ue n dditionl INV,, NAND nd NOR gte needed to implement thi unction. The completed gte hould onl hve input M, N, nd S nd put Z uch tht: i S = 0, Z = M XOR N i S = 1, Z = M XNOR N XOR XOR mol 0 1 mol Notice tht ou will hve to ue inverter to eliminte the need or inverted input (N or M ). ) Auming the h uilt-in control ignl inverter nd require 6 trnitor, how mn trnitor doe our deign require? To witch the XOR gte to n XNOR unction, we impl need to invert the input (or, lterntivel the input). I we let M e the input to the XOR gte, we need our circuit to p M i S = 0 or invert M i S = 1. There re mn w to do thi, ut n oviou choice might e to ue t oth the nd input o the XOR gte, o ignl S could pick which input to ue nd thu lter the unction rom XOR to XNOR. Thi i hown in Fig. A nd require 24 trnitor. Homework 1 Solution p. 5

6 S M N XOR Z Fig. A. Two to Prolem 6 A etter choice would e to eliminte one nd impl invert the put o the ter the hown in Fig. B. Thi require onl 20 trnitor. Check it nd mke ure ou ee how thi circuit meet the deign gol. S M N 0 1 XOR Z Fig. B. One to Prolem 6 Notice tht thi prolem we cn onl ue one XOR gte, ut i we were not limited to tht, more elegnt (ewer trnitor) might e ville. Tke look t the AND nd OR truth tle elow. Do either o them implement the unction M i S = 0, M i S = 1? No, the don t. But notice thi i ectl wht the XOR unction doe. Cn ou implement electle XOR/XNOR uing two XOR gte? I it ewer trnitor thn our deign? Homework 1 Solution p. 6

7 S M M AND S M OR S M XOR S Think A It: In thi coure, ou oten ee more thn one poile nd mut lern to nle the option to ind the et. Let think thi prolem. Wh would we wnt electle XOR/XNOR gte? Perhp o we could ue le circuitr to implement oth unction, reuing ingle XOR gte or multiple tk. Thi i ine ide nd one ou will wnt to conider oten, prticulrl in our deign project. The trightorwrd deign, implementing oth XOR nd XNOR unction in dierent gte, would require 1 XOR, 1 XNOR nd 1 (to elect etween put). Thi tke = 22 trnitor, plu 2 inverter (4 trnitor) to invert the nd input. Thi give u grnd totl o 26 trnitor. Did our ue ewer trnitor? Would the lterntive option with 2 XOR gte dicued ove ve trnitor? Once ou lern to nle the option nd mke the et choice to meet deign peciiction ou ll e well on our w to ecoming etter digitl circuit deigner. Homework 1 Solution p. 7