Aalborg Universitet. Published in: I E E E Transactions on Power Electronics. DOI (link to publication from Publisher): /TPEL.2015.

Transcription

1 Aalbrg Unverstet A New Way Cntrllng Parallel-Cnnected Inverters by Usng Synchrnus- Reerence-Frame Vrtual Impedance Lp Guan, Yajuan; Guerrer, Jsep M.; Zha, Xn; Qunter, Juan Carls Vasquez; Gu, Xaqang Publshed n: I E E E Transactns n Pwer Electrncs DOI (lnk t publcatn rm Publsher):.9/TPEL..779 Publcatn date: 6 Dcument Versn Accepted authr manuscrpt, peer revewed versn Lnk t publcatn rm Aalbrg Unversty Ctatn r publshed versn (APA): Guan, Y., Guerrer, J. M., Zha, X., Qunter, J. C. V., & Gu, X. (6). A New Way Cntrllng Parallel- Cnnected Inverters by Usng Synchrnus-Reerence-Frame Vrtual Impedance Lp: Part I: Cntrl Prncple. I E E E Transactns n Pwer Electrncs, 3(6), DOI:.9/TPEL..779 General rghts Cpyrght and mral rghts r the publcatns made accessble n the publc prtal are retaned by the authrs and/r ther cpyrght wners and t s a cndtn accessng publcatns that users recgnse and abde by the legal requrements asscated wth these rghts.? Users may dwnlad and prnt ne cpy any publcatn rm the publc prtal r the purpse prvate study r research.? Yu may nt urther dstrbute the materal r use t r any prt-makng actvty r cmmercal gan? Yu may reely dstrbute the URL dentyng the publcatn n the publc prtal? Take dwn plcy I yu beleve that ths dcument breaches cpyrght please cntact us at vbn@aub.aau.dk prvdng detals, and we wll remve access t the wrk mmedately and nvestgate yur clam. Dwnladed rm vbn.aau.dk n: august, 8

2 TPEL-Reg-379 A New Way Cntrllng Parallel-Cnnected Inverters by Usng Synchrnus Reerence Frame Vrtual Impedance Lp Part I: Cntrl Prncple Yajuan Guan, Student, IEEE, Jsep M. Guerrer, Fellw, IEEE, Xn Zha, Juan C. Vasquez, Senr Member IEEE, Xaqang Gu, Senr Member, IEEE Abstract A nvel smple and eectve autnmus current-sharng cntrller r parallel three-phase nverters s prpsed n ths paper. The prpsed cntrller prvdes aster respnse and better accuracy n cntrast t the cnventnal drp cntrl, snce ths nvel apprach des nt requre any actve r reactve pwer calculatns. Instead, a synchrnus-reerence-rame (SRF) vrtual mpedance lp and an SRF-based phase-lcked lp are used. Statnary analyss s prvded n rder t denty the nherent mechansm the drect and quadrature utput currents n relatn t the vltage ampltude and requency wth derent lne mpedances by means the system transer unctns. Cmparsn experments rm tw parallel nverters are presented t cmpare the cntrl perrmance the cnventnal drp cntrl and the prpsed cntrl wth derent lne mpedances. In addtn, expermental results rm a setup wth three parallel. kw nverters very the eectveness the prpsed cntrl strategy n derent scenars. Index Terms Parallel nverters, synchrnus reerence rame, phase-lcked lp, vrtual mpedance, drp cntrl. I. INTRODUCTION ROOP cntrl methd has been wdely used n the last Ddecade as the decentralzed cntrl parallel cnverters n several applcatns such as parallel redundant unnterruptble pwer supples (UPS) t avd crtcal cmmuncatn amng unts, dstrbuted pwer systems, mcrgrds (MGs), and s rth []-[]. Ths well-knwn cntrl technque ams t prprtnally share actve and reactve pwers whch adjustng requency and utput vltage ampltudes each nverter lcally n rder t emulate the behavr a synchrnus generatr [3]. Althugh ths technque nly requres lcal nrmatn, t presents a number Yajuan Guan, Jsep M. Guerrer, Xn Zha and Juan C. Vasquez are wth Department Energy Technlgy, Aalbrg Unversty, 9 Aalbrg, Denmark (e-mal: ygu@et.aau.dk, jz@et.aau.dk, xzh@et.aau.dk, juq@et.aau.dk). Xaqang. Gu, s wth the Key Lab Pwer Electrncs r Energy Cnservatn and Mtr drve Hebe prvnce, Department Electrcal Engneerng, Yanshan Unversty, Qnhuangda 66, Chna (e-mal: gxq@ysu.edu.cn) stablty ssues that have been slved alng the lterature []-[7]. One the man prblems s that the drp cecents whch regulate requency and ampltudes are bascally prprtnal terms, s that n rder t ncrease ther range values r mprvng system dynamcs, dervatve terms were added [3]-[6]. Unlke the cnventnal drp cntrllers whch yeld - dmensn reedm (DOF) tunable cntrl, the mprved drp cntrllers yeld -DOF tunable cntrl. Subsequently, the dynamc perrmance the system can be adjusted t damp the scllatry behavr the pwer sharng cntrllers wthut aectng the statc drp gans. Anther ssue wth regards t cnventnal drp s that the requency and vltage are respectvely related t actve and reactve pwer when the utput mpedance the generatr s manly nductve, e.g. nductn generatrs. Hence, by usng the drp methd, the pwer sharng perrmance s aected by the utput mpedance the dstrbuted generatn (DG) unts and the lne mpedances. Hwever, the utput mpedance can be xed by means a ast cntrl lp named vrtual mpedance n an nverter [7], [8]. In ths sense, the utput mpedance can be treated as anther cntrl lp whch enrces the nverter t behave n accrdance t the nductance-t-resstance rat (X/R) lne mpedance, e.g. manly resstve n case lw vltage netwrks [9]. In case resstve lnes and/r vrtual mpedances, the actve pwer s cntrlled by the nverter vltage ampltude, whle the reactve pwer lw s dmnated by the angle, s that t can be cntrlled by the requency the system []-[]. In ths sense, the actve pwer-vltage (P-V) drp cntrl needs t be used nstead the cnventnal actve pwer-requency (P-) drp cntrl, whch s cntrary t the cnventnal electrcal transmssn systems r nductn generatn dmnated systems. Several cntrl methdlges wth derent mplementatns r cnventnal drp cntrller have been als prpsed []-[8]. A Q V dt drp cntrl methd s mstly used t mprve reactve pwer sharng [9]. Based n the abvementned ssues, a cntrl archtecture based n a vrtual resstance, P-V and Q- drps s used r dealng wth the autnmus peratn parallel cnnected nverters [], [3]. Hwever, ths apprach has the nherent drawback that t needs t calculate nstantaneus actve and

3 TPEL-Reg-379 reactve pwers and then average them thrugh lw-pass lters (LPF) whse bandwdth deterrate the system transent respnse []. Even n three phase systems that the actve and reactve pwer can be calculated by usng the nstantaneus pwer thery, a pst-lter prcessng s necessary n rder t cmpletely remve the dstrted pwer cmpnents [3]. Furthermre, n a practcal stuatn, the lad sharng perrmance the cnventnal drp cntrl s degraded when shrt lnes wth small mpedance are used, especally n lw vltage netwrks. In ths case, a small devatn n vltage requency and ampltude wll result n large pwer scllatn and even nstabltes [3]. The drawbacks drp cntrl can be summarzed as lsted belw: Slw dynamc respnse: Snce t requres LPFs wth reduced bandwdth t calculate the average values the actve and reactve pwers bth n slanded and grd-cnnected mdes. Actve/reactve pwer cuplng. Slw respnses when actve/reactve pwer sharng rats are suddenly changed. Perrmance s serus aected by the lne mpedance. Cmplex desgn. The pwer sharng culd be degraded the sum the utput mpedance and the lne mpedance s unbalanced. Anther pssble slutn s the cmbnatn current sharng cntrl and pwer drp cntrl technques. A vltage-pwer drp/requency-reactve pwer bst (VPD/FQB) cntrl scheme whch allws multple vltage surce cnverters (VSCs) t perate n parallel n MGs and t share a cmmn lad pwer n prprtn t a predetermned ratn s presented n [33], [3]. In [33], an addtnal vrtual resstance lp s necessary snce the nverter utput mpedance cannt be equal t zer due t the PI cntrller n vltage cntrl lp. A decentralzed cntrl r redundant parallel cnnectn multple UPS usng nly current sensrs s prpsed [3], [36]. The actve and reactve cmpnents utput current are used nstead actve and reactve pwer t mmc the drp cntrl, whle the LPFs are stll necessary. A nvel pecewse lnear V-I drp cntrller has been prpsed t explt the lexblty and ast dynamcs the nverter-based dstrbuted energy resurces [37], hwever a glbal pstnng system (GPS) sgnal as the cmmuncatn s used t synchrnze each DG unt and allw r cnstant requency peratn. A vltage and requency drp cntrl based n mxed vltage and current surce cncept and nte utput mpedance emulatn r sngle phase nverter based lw vltage grd has been prpsed [], [38]. Ths methd can prvde nt nly wreless parallel peratn cntrl, but als has the capablty mtgatn vltage harmncs and shrt-crcut behavr as t takes the R t X lne mpedance rat nt accunt. Hwever, ths cntrl apprach s cmplex, snce a Kalman lter estmatr and a lnear quadratc regulatr are requred. T cpe wth all the arementned, a smpler and aster cntrller s prpsed n ths paper, whch cnssts a synchrnus-reerence-rame (SRF) vrtual mpedance lp, an SFR phase-lcked lp (PLL) and a prprtnal-resnant (PR) cntrller n vltage cntrl lp. The prpsed cntrl strategy prvdes bth nstantaneus current sharng and ast dynamc respnse r paralleled vltage cntrlled nverters (VCIs). The vrtual resstance lp whch cntans a d-axs vrtual resstance lp and a q-axs vrtual resstance lp s used t acheve drect and quadrature lad currents sharng separately amng three-phase nverters. The cncept s derved rm the current-sharng cntrl schemes already used n dc paralleled cnverters [39]-[]. In cntrast wth the cnventnal drp cntrl, there s n need t calculate actve/reactve pwers. An addtnal PLL s needed t adjust the phase the vltage reerence and ensure the synchrnzatn amng the paralleled VCIs. The paper s rganzed as llws. Sectn II revews the cnventnal drp cntrl prncple. Sectn III analyzes the current lw when vrtual resstve mpedance n the statnary reerence rame s used. Sectn IV ntrduces the prpsed cntrl structure and the cntrl prncple. Sectn V presents the nherent drp characterstc and cuplng analyss the prpsed cntrl wth derent lne mpedances. Expermental results are shwn n Sectn VI n rder t evaluate the easblty the prpsed apprach and t cmpare the cntrl perrmance wth the cnventnal drp cntrl. Sectn VII cncludes the paper. Fnally, the appendx prvdes the dervatve prcess the mathematc equatns. Ths paper s the rst part a tw-part paper cusng n the cntrl prncple and steady state perrmance analyss. The secnd part ths paper deals wth the small-sgnal state-space mdels and stablty analyss the prpsed parallel-vci-based system. II. REVIEW OF THE DROOP CONTROL PRINCIPLE Fg. shws the equvalent crcut a tw-paralleled nverter system ncludng generated vltages ( and ), utput mpedances ( and ), vrtual mpedances ( vr and vr Z ), utput vltage ( and ) and lne mpedances ( Z and ) each nverter. It can be cnsdered as a lne lne subset dstrbuted pwer netwrk peratng n autnmus slanded mde. The phase derences between the utput vltage (ϕ gn) and the pnt cmmn cuplng (PCC) vltage (ϕ bus), as well as the ampltude equvalent mpedance ( Zn ϕn ), whch cnssts nverter utput mpedance ( Zn ϕzn ), lne mpedance ( Zlnen ϕlnen ), and vrtual mpedance ( Zvrn ϕvrn ), are cnsdered n ths study. The actve and reactve pwer utput can be derved as: V gn csϕn VgnVbus cs( ϕgn ϕbus + ϕn ) Pn = () Z Q Z n Z Z V V n V gn snϕn VgnVbus sn( ϕgn ϕbus + ϕn ) = () Z In tradtnal pwer systems, the equvalent mpedances between the paralleled nverters present hgh X/R rat. The n V g V g Z

4 TPEL-Reg V Z I Z vr Z V lne g Z I vr V Z V Z lne g Vbus Z lad G (s) V n ren (s) R vrn (s) I n (s) V bus Fg.. Equvalent crcut a parallel nverter system wth vrtual resstances. Fg.. Equvalent Thévenn crcut clsed-lp nverter. actve pwer ( P n ) can be adjusted wth the vltage angle (ϕ gn), and reactve pwer ( Q n ) can be regulated wth vltage ampltude (V gn ) separately. Based n ths pwer lw analyss, the drp cntrl law can be expressed as: I R q vrq I R q q vrq ΔV ΔV ω = ω + k ( P P ) * * n n pω n n V = V + k ( Q Q ) * * n n qv n n (3) () Fg. 3. Vectr dagram the cncept. θ θ Id Rvrd IdRvrd d * ω n * V n where and are the nrmal angular requency and utput vltage ampltude, respectvely, k p ω and k qv are the drp cecents. Hwever, the lad sharng perrmance the cnventnal drp cntrl s degraded n a practcal stuatn when usng shrt lnes wth small mpedances, especally n lw vltage netwrks. Output pwer ( Pn and Qn ), utput vltage ampltude and requency are cupled, because [ sn( ϕn ϕbus )]/ Z n ( ϕn ϕbus ) / Z n cannt be neglected when ϕn ϕbus r Z n s t small, that may result n mprecse pwer cntrl. Furthermre, the stablty prblems wuld arse r cnventnal drp cntrlled systems wth small equvalent lne mpedance Z n, snce small requency r vltage ampltude devatns can result n large pwer scllatns. III. CURRENT FLOW ANALYSIS Each nverter n Fg. can be mdeled by a tw-termnal Thévenn equvalent crcut n Laplace as llws: [ ] V (s) = G (s) V (s) Z (s) + Z (s) + Z (s) I (s) () bus n ren n lnen vrn n where V ren (s) s the utput vltage reerence; Gn () s s the vltage gan. The nner current and vltage lps are respnsble r mnmzng Zn () s,. e. by usng a prprtnal + resnant (PR) cntrller tuned at the lne requency. In ths sense, Zn () s s apprxmately equal t zer, whereas G n(s) s equal t at the resnant requency PR cntrller. Cnsderng that Zlnen () s s practcally very small n lw scale systems such as lw vltage MGs, Z vrn (s) becmes the predmnant cmpnent. Thus, () can be smpled as: V (s) = G (s) V (s) Z (s) I (s) (6) bus n ren vrn n When nly vrtual resstance s adpted, an equvalent Thévenn crcut can present the clsed lp nverter, as llustrated n Fg.. The vltage derence between the generated vltage and cmmn bus vltage at the lne requency can be expressed n dq reerence rame as llws: V V = I R + ji R (7) ren bus dn vrdn qn vrqn where I dn and I qn are the d and q-axs cmpnents utput current, respectvely. In ths case, because the vltage reerence phasr ( V re ) and cmmn bus vltage phasr ( V bus ) are dentcal r each DG unt, the derent values R vrd and Rvrq wll result n derent vltage drp that wll cause derent current utput vectrs ( I ), as shwn n Fg. 3. The relatnshp I d, I q, R vrd and R vrq can be generalzed and expressed r number N cnverters as llws: I R I R I R d vrd = d vrd =... = dn vrdn q vrq = q vrq =... = qn vrqn I R I R I R (8a) (8b) The d- and q-axs utput currents I d and I q the paralleled nverters are nversely prprtnal t the crrespndng vrtual resstances. Therere, the drect and quadrature currents utput each nverter can be regulated ndependently by adjustng the vrtual mpedances based n derent pwer rates, cmmands rm energy management system (EMS) r ther superr cntrl lps. Furthermre, the actve and reactve pwer utput sharng strategy amng the paralleled nverters can be btaned rm (8) by multplyng the vltage reerence. Hence, cnsderng that the vltage reerences (V re ) each nverter are equal, the actve and reactve pwer utput wll als be prperly shared based n the vrtual resstances, as shwn n (9): PR = PR = = P R (9a) vrd vrd N vrdn Q R = Q R = = Q R (9b) vrq vrq N vrqn

5 TPEL-Reg-379 where P n and Q n are the actve and reactve pwer utput nverter #n. IV. PROPOSED AUTONOMOUS CURRENT-SHARING CONTROLLER Fllw the abve analyss, a smpler and aster cntrller s prpsed n ths paper. The nvel cntrl strategy s shwn n Fg. (b). Cmpared wth the mprved drp cntrller n Fg. (a), the drp cntrller culd be replaced by a nvel cntrller whch cmprses an SRF-PLL and a vrtual resstance lp n SRF. A. Cnguratn the prpsed cntrller The pwer stage cnssts a three-leg three-phase nverter cnnected t a DC lnk, laded by an L -C lter, and cnnected t the AC bus thrugh a pwer lne (Z lne ). Indeed, the prpsed cntrl strategy can als be extended t sngle-phase systems. The man derence between the sngle-phase systems and three-phase systems s that the rthgnal vltage system n sngle-phase systems needs t be generated by an extra cntrl lp [3], []. The cntrller ncludng an SRF-PLL, a vrtual resstance lp (R vrd and R vrq ), a DC lnk vltage eed-rward lp, and the cnventnal PR nner vltage and current cntrllers (G v and G ) generates a PWM sgnal t drve the IGBT nverter gates. Inductve currents and capactr vltages are transrmed t the statnary reerence rame ( Lαβ and vc αβ ). Output currents are transrmed t the SRF ( dq ). The drect and quadrature utput currents are ndependently cntrlled by the vrtual mpedance lp n dq axs. The nner vltage and current lps are mplemented n αβ reerence rame snce the PR cntrller can deal wth bth pstve and negatve sequence vltage when the negatve sequence vltage and current appear. Fg. shws the smpled prpsed cntrl blck dagram, whch ncludes the three-leg three-phase nverter, L -C lter, lne mpedance, vrtual mpedance lp, the PLL and the nner vltage and current cntrl lps. The clsed lp transer unctn T plant (s) can be descrbed as llws: T plant V () s ( s) = Vre () s () Gs () + GLequ () szlne () s = + G ( s) Z ( s) + G ( s) G( s) + G ( s) Z ( s) Lequ lne vr Lequ beng G () s G() s K Gs () = LCs rc G sk C G sg sk sl + r Z() s = LCs + ( rc + G() sk C )s+ + G() sg() sk Kvs Gv() s = Kpv +, G () s = Kp, GLequ s + ω ( s ) = + c RLequ sl R R vrd vrq Zlne () s = Rlne + sllne, Gvr( s) = + R sl v PWM + ( + () PWM )s+ + v() () PWM PWM v PWM where G(s) presents the trackng perrmance the utput vltage llwng the vltage reerence, Z() s s the equvalent utput mpedance the nverter, Zlne() s s the lne mpedance, R lne s the lne resstr, L lne s the lne nductance, G () Lequ s s the equvalent lad admttance, R Lequ s the equvalent resstr, L Lequ s the equvalent nductance, V () s s the utput vltage, Vre () s s the reerence vltage, () s s the utput current, Gv () s s the PR vltage cntrl lp, G () s s the prprtnal current cntrl lp, K PWM s the gan three phase nverter, L, C and r are the nductr, capactr, and nductr ESR LC lter respectvely, K pv and K v are the prprtnal and ntegral cecents vltage cntrl lp, ω s the resnant requency the PR vltage cntrl lp, c K s the prprtnal cecents current cntrl lp, p R vrd and R vrq are the d-axs and q-axs vrtual resstrs. The detaled dervatve prcess s prvded n the Appendx. B. Cntrl Prncple The prpsed cntrller supples a reerence vltage t the Lequ Lequ Lequ dclnk v dc PWM x abc αβ INVERTER I INVERTER II L abc αβ L αβ L C c n G () s Gv () s Inner lp Drp CONTROL dq αβ v αβ αβ dq abc dq v dq s ω θ v re generatr Drp cntrller Z vr Vrtual mpedance v re P/ Q Q P abc abc dq dq m n * ω * V Z lne Z lne s AC bus s. Z lad dclnk v dc PWM x abc αβ INVERTER I INVERTER II L abc αβ L αβ G() s G () s Inner lp L C c v n PROPOSED CONTROL (a) Fg.. Cntrl structure cmparsn between (a) the cnventnal drp cntrl and (b) the prpsed cntrl methd. abc αβ v αβ Δv αβ abc dq PI v re v re generatr d abc αβ dq dq αβ q R vrq SRF vrtual mpedance lp (b) R vrd ω base θ s PLL θ abc αβ αβ Z lne Z lne s AC bus s. Z lad

6 TPEL-Reg-379 V re Vre snθ v re ' v re G(s) v Bde Dagram Tplant () s R vrd R vrq Fg.. Smpled cntrl blck dagram. Z lad d q Z lne R Lequ sl Lequ v bus Phase (deg) Magntude (db) System: GLPF Frequency (rad/s): 3. Magntude (db): -3. System: GPLL Frequency (rad/s):.e+3 Magntude (db): -3. Magntude (db) Phase (deg) Frequench (Hz) Fg. 6. Bde dagram the system transer unctn. nner lp. The vltage reerence V re. s generated by cmbnng the ampltude reerence ( V re ) and the phase generated (θ ) by the PLL. Even thugh the PLL s tryng t synchrnze the nverter wth cmmn AC bus, n case supplyng reactve lads, the quadrature current lwng thrugh the vrtual resstance wll prduce an unavdable quadrature vltage drp, whch wll cause an ncrease n PLL requency. In ther wrds, the PLL wll cmpel the nverter t be stablzed at a requency pnt wth zer phase delay (ZPD) btaned rm the system transer unctn. The requency ZPD s aected by the quadrature current as shwn n Fg. 6. Thus, the mechansm nherently endws an Iq ω drp characterstc n each nverter. Smlarly, n case supplyng actve lads, the drect current lwng thrugh the vrtual resstance wll drp the drect vltage, causng a decrease n the utput vltage ampltude. Hence, a drp characterstc s als mpsed by the vrtual resstance adaptng the ampltude utput vltage, whch endws t the system an I d V drp characterstc. Mrever, the settlng tme can be cnsderably mprved because the prpsed cntrller des nt requre any pwer calculatn. The bandwdth the PLL can be desgned thrugh the lnearzed mdel [], [6] t be hgher than the bandwdth the LPF that s used r PQ calculatn purpses n the 3 3 Frequency (rad/s) Fg. 7 Bde dagram the PLL (red lne) and the LPF (blue lne) cnventnal drp cntrller [7]. The cut requency the LPF n the pwer drp cntrl lp s usually preassgned t 3 rad/s t btan the average pwer whle avdng undesrable nteractn [], [6]. The bandwdth the PLL n the prpsed cntrl s rad/s when k p_pll and k _PLL are equal t. and respectvely. The Bde dagram s shwn n Fg. 7. Hwever, the astest transent respnse PLL shuld be almst equal t the transent respnse speed the nner vltage cntrl lp t ensure the system stablty. V. INHERENT DROOP CHARACTERISTIC AND COUPLING ANALYSIS Cnsderng the nherent mechansm I d wth vltage ampltude and I q wth requency, tw vrtual resstances R vrd and R vrq are emplyed t share the quadrature and drect lad currents amng the nverters ndvdually. I q A. sharng When the nverters and lads all cnnect t the cmmn AC bus, the prpsed cntrller wll make the system stable at a requency-stable peratn pnt whch may has a small devatn rm Hz. The small devatn s determned by the unctn PLL, R vrq and I q. The requency-stable peratn shuld be the crss zer pnt the phase-requency characterstcs the clsed-lp transer unctn the system, as depcted n the dashed part n Fg.. Therere, the parallel nverters wll perate n the same system requency, but wth derent phase angles that depend n the utput quadrature current and q-axs vrtual resstance value. Based n (), as s = jω, the relatnshp R vrd, R vrq, I d, I q and angular requency ( ω ) can be calculated based n arctan Tplant ( jω) = ()

7 TPEL-Reg In rder t analyze the relatnshp Rvrq, I q and ω, Rvrd and Id are preset t a xed value. The relatnshp Rvrq, I q and ω wth derent lne mpedances s shwn n Fg. 8. Fgs. 8 (a.) and 8 (b.) shw the relatnshp wth zer lne mpedance. Fgs. 8 (a.) and 8 (b.) descrbe the relatnshp wth resstve-nductve lne mpedance (L lne =.7 mh, R lne = Ω). Fgs. 8 (a.3) and 8 (b.3) present the relatnshp wth purely nductve lne mpedance (L lne =.8 mh). The nherent mechansm the prpsed I q ω drp cntrller wth derent lne mpedances are depcted n Fgs. 8 (b.), 8 (b.) and 8 (b.3). Fg. 8 ndcates that the lne mpedances n ths range barely have eect n the relatnshp R, and, as well as I q ω vrq I q ω drp characterstcs. Ths s because the nluence the nductve lne mpedance n ths range has been cmpensated by the vrtual resstrs. As bserved n Fgs. 8 (b.), 8 (b.) and 8 (b.3), the quadrature current sharng amng the parallel nverters can be adjusted by regulatng the q-axs vrtual resstance rat. By cntrast, the relatnshps varables Rvrd, Id and ω wth derent lne mpedances are derved by assgnng R vrq and I q t certan values. The relatnshps Rvrd, Id and ω wth zer, resstve-nductve, and purely nductve lne mpedance are shwn n Fgs. 9 (a.) t 9 (a.3) respectvely. Addtnally, Fgs. 9 (b.), 9 (b.) and 9 (b.3) are btaned by assumng R vrd t derent values based n the relatnshps Rvrd, Id and ω under derent lne mpedance cndtns. As bserved rm Fgs. 9 (b.) t 9 (b.3), the nluence drect utput current n angular requency changes by an expnental dependence when t gettng clser t the resnance requency PR cntrller, whch means that the mpact R and I n ω can be neglected. vrd d B. sharng I d In rder t share actve lads, the parallel nverters wll have derent utput vltage ampltude devatns rm the vltage ampltude reerence V re, whch depend n the utput drect current and d-axs vrtual resstance value each nverter. The vltage drp ( ΔV ) can be dvded nt tw parts as llws: Δ V = I R + V T ω ' d vrd re plant (j ) () where the ω ' s the angular requency requency-stable peratn pnt. The rst part () s the prduct d-axs vrtual resstance Rvrd and drect current utput Id, whch dmnantly aects the utput vltage ampltude drp. The secnd part () s caused by the magntude attenuatn clsed-lp transer unctn whch results rm the small but nnlnear requency devatn due t the characterstc PR cntrller. Hwever, as dscussed abve, the system requency wll be stable and the devatns amng the parallel nverters wll be equal t each ther, that s, the vltage devatns resultng rm the secnd part () are als the same amng nverters. Therere, the nluence n the devatns can be neglected. Thus, the per-unt value utput vltage ampltude can be derved rm () as llws: = T (s) = ( I, I, R, R, ω) (3) The parameters R and I are xed t analyze the Zer lne mpedance Resstve-nductve lne mpedance Purely nductve lne mpedance V V re plant d q vrd vrq vrq q Iq (A) (a. ) (a. ) (a. 3) (b. ) (b. ) (b. 3) Fg. 8. The relatnshp Rvrq, Iq and ω wth derent lne mpedances. (a) The relatnshp Rvrq, Iq and ω wth derent lne mpedances, (b) The relatnshp I and ω when R vrq=ω/ω wth derent lne mpedances. q

8 TPEL-Reg Zer lne mpedance Resstve-nductve lne mpedance Inductve lne mpedance ω (rad/s) R vrd (Ω) - (a. ) (a. ) (a. 3) (b. ) (b. ) (b. 3) Fg. 9. The relatnshp R vrd, Id, and ω wth derent lne mpedances. (a) The relatnshp R vrd, Id, and ω wth derent lne mpedances, (b) The relatnshp I and ω when R vrd=ω/ω wth derent lne mpedances respectvely. d relatnshp R, I and V. The relatnshp R, vrd d Id and V wth zer, resstve-nductve, and purely nductve lne mpedances lne mpedance are shwn n Fg.. As t can be seen that the lne mpedances n the certan range barely have eect n the relatnshp R, I and V. Fgs. (b.) t vrd (b.3) shws the nherent Id V drp mechansm the prpsed cntrller under derent lne mpedance cndtns. As bserved, as the utput drect current ncreases, the vltage ampltude decreases wth derent rat V d I d vrd crrespndng t derent R vrd values. Thus, the drect current sharng amng the parallel nverters can be adjusted by regulatng the d-axs vrtual resstance rat. Smlarly, R, I are xed t analyze the eect requency devatn n the vltage ampltude wth derent lne mpedances. The relatnshps Rvrq, ω and V wth zer, resstve-nductve, and purely nductve lne mpedance are shwn n Fgs. (a.) t (a.3) respectvely. Fgs. (b.) t (b.3) ndcate that the relatnshp V ω almst mmune Zer lne mpedance Resstve-nductve lne mpedance Purely nductve lne mpedance R vrd (Ω) vrd d V V (p.u.) (a. ) (a. ) R vrd = I d (A) (b. ) (b. ) (b. 3) Fg.. The relatnshp Rvrd, Id and V wth derent lne mpedances. (a) The relatnshp R, and wth derent lne mpedances, (b) The vrd Id V relatnshp I and V when R vrd=ω/ω wth derent lne mpedances respectvely. d R vrd = I d (A) (a. 3)

9 TPEL-Reg t bth R vrq and derent lne mpedances. The eects Rvrq and ω n V are nnlnear but qute small n cmparsn wth the vltage drp caused by adjustng R vrd and Id. Cnsderng that the vltage drp caused by Δω, s apprxmately the same n each nverter, t can be neglected. Cnsequently, t can be bserved a very well decuplng between I d and I q r a large set X/R rats (rm purely X t purely R). C. Vrtual mpedance desgn The vrtual mpedances n the prpsed cntrl lp are used t generate the drect and quadrature vltage devatns by multplyng the drect r quadrature currents separately. The drect and quadrature vltage devatns are used t autmatcally adjust the ampltude and phase angular nverter utput vltage. Gven that vrtual mpedances nduce utput vltage and requency devatn, they shuld be chsen t ensure that the vltage and requency devatns are n the permssble range. Fr example, the maxmum vltage devatn (ΔV max ) s %, whle the maxmum requency devatn (Δ max ) s. Hz n a lw vltage netwrk. The relatnshp between the maxmum vltage magntude devatn ΔV dmax and I d can be derved as llws: Δ V = R I () dmax vrd d In an extreme case, the nverter s assumed t supply nly actve current. () can be presented as llws: where, d _ max Δ V = R I () max vrd _ max d _max I s the maxmum d-axs current the nverter. Thus, the upper lmtatn the d-axs vrtual resstr can be descrbed as llws: R ΔV max vrd _max = I (6) _ rate Smlarly, n an extreme case, the nverter s assumed t supply nly reactve current. The relatnshp between the maxmum angular requency ω max, quadrature utput current I q and R vrq can be derved rm (), as expressed n (7): max R vrq _max num = (7) den beng: num = Vre ωmax ( ωmax ω )[ Kv (+ C L ωmax ) + CKpv( KpKPWM + r)( ωmax ω )], den = Iq _ max Kp KPWM [ ωmax ( Kv + Kpv ωmax ) + K ω ( ω ω )] pv where V re s the vltage reerence magntude, ω s the undamental requency, K PWM s the gan three-phase nverter, and I s the maxmum d-axs current utput d _ max the nverter. Ths relatnshp s mre cmplex than the relatnshp ΔV dmax, I d_max and R vrd_max because the requency the prpsed system s aected nt nly by the vrtual resstance and quadrature current but als by the PR vltage cntrl lp. Based n (7), the maxmum q-axs vrtual resstance can be calculated. On the ther hand, anther unctnalty the vrtual Zer lne mpedance Resstve-nductve lne mpedance Purely nductve lne mpedance ω (rad/s) R vrd (Ω) (a. ) (a. ) (a. 3) (b. ) (b. ) (b. 3) Fg.. The relatnshp Rvrq, ω and V wth derent lne mpedances. (a) The relatnshp R, and wth derent lne mpedances, (b) The vrq ω V relatnshp ω and V when R vrq=ω/ω wth derent lne mpedances respectvely

10 TPEL-Reg dspace 6 Danss Inverters Resstve lad Inductve lad (a) Lne mpedance Lne mpedance Resstve lad Fg. 3. Expermental setup Fg.. The relatnshp I q and ω when the lne mpedances are equal t the maxmum values. (a) L lne s equal t 6 mh, (b) R lne s equal t Ω. resstance s t cmpensate the eects lne nductance. Thus, the vrtual resstr shuld nt t small t predmnate ver the utput mpedance the cnverter. D. The lmtatns the lne mpedance The lmtatns the lne mpedance depend n the cntrl lp parameters, the vrtual mpedance and electrcal parameters. In ths case, the R vrd and R vrq are bth equal t Ω, the maxmum nductve lne mpedance and the maxmum resstve lne mpedance that are able t mantan the steady state peratn the prpsed parallel-nverter based system can be calculated by (). The maxmum nductve lne mpedance and the maxmum resstve lne mpedance are apprxmately 6 mh and Ω respectvely. The prpsed Id V and Iq ω drp characterstcs wll present nn-lnear when the lne mpedance ver the lmtatns, as llustrated n Fg.. In general, the prpsed cntrl strategy can prvde gd cntrl perrmance ver a wde range lne mpedance whch s hard t acheve by prevusly develped cntrl strateges. VI. EXPERIMENTAL RESULTS An slanded expermental MG setup, whch cnssts three Danss. kw nverters, a real-tme dspace6 platrm, LC lters, lne mpedance, resstve lad and resstance -nductance lad has been bult accrdng t Fg., as shwn n Fg. 3. The swtchng requency s set t khz. The electrcal setup and cntrl system parameters are lsted n Table I. Derent scenars have been cnsdered t test the perrmances the prpsed cntrller. In addtn, a tw parallel-nverters system has been used t cmpare and evaluate the perrmance the prpsed cntrl apprach (b) DG Inverter and utput lter Lads (Fgs. 6 and 7) Inner Lp Drp Cntrl Prpsed Cntrl Lads (Fgs. and ) TABLE I POWER STAGE AND CONTROL SYSTEM PARAMETERS Parameters Value Descrptn V dc DC vltage 6 V V MG MG vltage 3 V MG requency Hz s Swtchng requency khz L Flter nductance.8 mh C Flter capactance µf L lne_ Resstve nductve lne Ω +.7 mh L lne_ Inductve lne.8 mh Z lad Lcal lad 7+j.83 Ω Z lad Lcal lad 7 Ω k p Current prprtnal term.7 K Current ntegral term K pv Vltage prprtnal term. K v Vltage ntegral term 9 k pp Actve pwer drp prprtnal cecent e-7 k P Actve pwer drp ntegral cecent 6e-6 k pq Reactve pwer drp prprtnal cecent e k Q Reactve pwer drp ntegral cecent R v Vrtual resstance Ω L v Vrtual nductance 8 mh K p_pll PLL prprtnal term. K _PLL PLL ntegral cecent R vrd d-axs vrtual resstance (nverter ) Ω R vrq q-axs vrtual resstance (nverter ) Ω R vrd d-axs vrtual resstance (nverter ) Ω R vrq q-axs vrtual resstance (nverter ) Ω Z lad Lcal lad 3+ j.83 Ω Z test Step up lad 6 Ω wth the cnventnal drp cntrl. In ths cmparsn, the parameters electrcal and nner vltage and current lps are all the same r bth cntrl methds.

11 TPEL-Reg-379 A. Cmparsn experment wth nductve lne mpedance Fg. shws the expermental results t cmpare the cntrl perrmance the cnventnal drp cntrl and the prpsed cntrl wth purely nductve lne mpedance whch s equal t.8 mh n three derent scenars. Fgs. (a.) t (a.6) shws the transent respnse when VCI # s cnnected t VCI # wth the cnventnal drp cntrller and the prpsed cntrller separately. As seen n Fgs. (a.) t (a.), VCI # s cnnected t a resstve-nductve lad eedng arund (.6+j.) A, whle VCI # s dscnnected. At.3 s, VCI # s cnnected t VCI #, peratng n parallel supplyng a cmmn lad. The drect and quadrature currents utput VCI # are ncreased by.8 A and. A respectvely, whereas the utput drect and quadrature currents the VCI # are decreased als by.8 A and. A respectvely. The settlng tme s apprxmately. s wth the cnventnal drp cntrl, whereas the settlng tme s apprxmately s wth the prpsed cntrl strategy. Ntce that a small versht ccurs due t small vltage errr between nverters at the mment cnnectn, as shwn n Fg. (a.3). An set apprxmately.3 A reactve current when usng the drp cntrl can be und n Fg. (a.3) due t the unbalance between lne mpedances, whch s well suppressed when usng the prpsed cntrller as shwn n Fg. (a.). Fg. (a.) shws that ater. s the system requency at 9.99 Hz was restred clsely t Hz because the decrease the utput currents wth cnventnal drp cntrl. As can be bserved n Fg. (a.6), the system requency at.3 Hz was restred t.8 Hz. All these devatns n bth cases are mantaned wthn the acceptable range, e.g., ±. Hz. Fg. (b.) t (b.6) shws the transent respnse durng lad step changes n the AC cmmn bus. At the begnnng, the parallel VCIs perate wth same pwer rates. At.3 s, an extra 6 Ω resstve lad s cnnected t the cmmn bus. The drect currents utput VCI # and VCI # bth ncrease by.3 A mmedately t supply the needed current wth cnventnal drp cntrl and the prpsed cntrller as shwn n Fgs. (b.) and (b.). The quadrature currents utput VCI # and VCI # wth the cnventnal drp cntrl devate by apprxmately.3 A because the cuplng between drect and quadrature currents as shwn n Fgs. (b.3). Hwever, by usng the prpsed methd the quadrature currents utput VCI # and VCI # can mantan ther rgnal values, beng barely aected by the drect utput current dsturbances as shwn n Fgs. (b.). The requency respnse t lad dsturbances r bth VCI unts s depcted n Fgs. (b.) and (b.6). The transent respnse r sudden drect currents sharng rat changes between the parallel VCIs s llustrated n Fgs. (c.) t (c.6). At the begnnng, the VCI unts parallel perate wth a cmmn RL lad. Bth the VCI # and VCI # eeds are apprxmately.8 A drect current and. A quadrature current. At.3 s, the drect current sharng rat between the parallel VCIs wth the cnventnal drp cntrl has been suddenly changed rm : t : and then changed back t : at.6 s. As t can be seen n Fg. (c.), ater abut maxmum 6 s, the utput currents the parallel VCIs are changed accrdng t the new sharng rat. Meanwhle, the quadrature current sharng has been aected by the changes n drect current sharng rat as shwn n Fg. (c.3). By cntrast, the drect current sharng rat between the parallel VCIs wth the prpsed cntrl apprach has als been suddenly changed rm : t : at.6 s and then changed back t : at 3. s. Fg. (c.) shws that the drect current utputs VCIs ncrease mmedately accrdng t the sharng rat changes and the transent respnse nly lasts. s. Meanwhle, the quadrature current sharng rat s kept cnstant va the decuplng cntrl the prpsed cntrller. B. Cmparsn experment wth resstve-nductve lne mpedance Fg. shws the expermental results n rder t cmpare the cnventnal drp cntrl and the prpsed cntrl, wth resstve-nductve lne mpedance whch s equal t Ω plus.7 mh n three derent scenars. Smlarly Fgs. (a.) t (a.6) shw the transent respnse drect currents, quadrature currents and requency when the VCI # s cnnected t VCI # wth the cnventnal drp cntrller and the prpsed cntrller separately. Fgs. (b.) t (b.6) llustrate the transent respnse r lad step-up changes n AC cmmn bus. Fgs. (c.) t (c.6) present the transent respnse durng sudden drect currents sharng rat changes between the parallel VCIs. Bth the cnventnal drp cntrl and the prpsed cntrller can acheve stable peratn. By cntrast, the prpsed apprach can endw the system wth aster respnse speed, smaller versht and decuplng cntrl. Oscllatn appears n the utput current and system requency wth the cnventnal drp cntrl due t the resstve-nductve lne mpedance and the cuplng between I d and I q. When havng almst zer lne mpedance, r hghly resstve, the parallel VCIs cannt perate by usng the cnventnal drp cntrl. In cntrast, excellent perrmance can be btaned by usng the prpsed cntrl as shwn belw. Fr the rest the tests, three parallel nverters have been cnsdered t test the perrmances the prpsed cntrller wth zer lne mpedance n the llwng scenars. C. Ht-swap peratn (zer lne mpedance) A three-parallel VCIs system sharng a lnear lad (R lad =7+j.83 Ω) tests have been dne t test ndvdually the eects DG unts cnnectng and dscnnectng. The transent respnse the nstantaneus currents, drect and quadrature utput currents and requency wth the prpsed cntrl are llustrated n Fg. 6 (a), (b) and (c), respectvely. As t can be bserved, at the begnnng, the three VCI unts are n parallel peratn wth same pwer rates. At t and t 3, VCI # and VCI #3 are dscnnected rm VCI # separately, whereas VCI # s respnsble r supplyng the ttal current. Fg. 6 ndcates that the utput currents VCI # and VCI #3 decrease t zer, meanwhle, the utput currents VCI # s ncreased t 7. A mmedately. Ater the synchrnzatn prcess, VCI # and VCI #3 are re-cnnected t VCI # at t and t respectvely. The transent perrmance s smth and ast that the slwest settlng tme s abut.8s. Furthermre, the current scllatns are well damped.

12 TPEL-Reg d Inverter cnnectn Lad step changes Rat changes Drp cntrl d d -.8 d 3 (a. ) (b. ) (c. ) d -. d -.8 d d d d (a. ) (b. ) (c. ). q -. Drp cntrl q q q (a. 3) (b. 3) (c. 3).. -. q q q q q q (a. ) (b. ) (c. ) Drp cntrl (a. ) (b. ) (c. ) (a. 6) (b. 6) (c. 6) Fg.. Cmparsn expermental results wth purely nductve lne mpedance n derent scenars q Drp cntrl Drp cntrl Drp cntrl d Drp cntrl -.8 d q Drp cntrl Drp cntrl

13 TPEL-Reg-379. d -. Inverter cnnectn Lad step changes Rat changes d (a. ) d d 3 (b. ) d -.8 d (c. ). d -. d (a. ). q q (a. 3). q q (a. ) d -.8 d 3 (b. ) q q (b. 3) q -. q -. 3 (b. ) d d q (c. ) -. q q q (c. 3) 3 (c. ) (a. ) (a. 6) (b. ) (b. 6) Fg.. Cmparsn expermental results wth resstve-nductve lne mpedance n derent scenars (c. ) (c. 6)

14 TPEL-Reg () () I (A) I (A) I3 (A) (a) t t t 3 t t t 6 () () Id (3) Id3 () Id (3) () () () () (3) Iq3 (). (3) () Iq Iq () (b) (c) Fg. 6. Transent respnses DG, DG, and DG3 n cnnectn and dscnnectn scenar wth the prpsed cntrller. (a) Instantaneus utput currents DG-3, (b) Drect and quadrature utput currents DG-3, (c) Frequency DG-3.

15 TPEL-Reg-379 D. Drect and quadrature currents decuplng sharng wth derent sharng rat (zer lne mpedance) In sme cases, the parallel cnnected VCIs need t supply actve and reactve currents wth derent rates based n derent pwer rates, requrements rm EMS r ther superr cntrl lps. A three- parallel VCIs setup sharng a cmmn dstrbuted lnear lad (R lad =7+j.83 Ω) has been bult t test the decuplng sharng perrmance drect and quadrature currents wth derent sharng rats. As shwn n Fg. 7, the experment can be dvded nne stages. The derent stages (S t S9) are descrbed as llws: S (t -t ): The three VCIs are n parallel peratn t share the cmmn lad equally due t the same vrtual resstances S (t -t 3 ): The d-axs vrtual resstance (R vrd ) rat these three paralleled VCIs s suddenly changed rm :: t.:: at t. Thus, the drect current utput VCI # s decreased mmedately, whereas the drect currents utput VCI # and VCI #3 are all ncreased by the same value wthn.s. The change n actve current des nt nluence n the quadrature currents these three VCIs as the theretcal analyss. S3 (t 3 -t ): The R vrd rat s suddenly changed rm.:: t.:.: at t 3. As bserved, the utput drect current VCI # s decreased t the desred value. S (t -t ): At t, the paralleled system s subjected t a % step up n the q-axs vrtual resstance (R vrq ) VCI #. Thus, the R vrq rat these three VCIs s suddenly changed rm :: t :.:. As bserved, the utput quadrature current rat becmes.::. whch s the nverse prprtn the vrtual resstance rat as the theretcal analyss. In addtn, the change n reactve current als des nt aect the drect currents. S (t -t 6 ): The R vrq rat suddenly changes rm :.: t :.:.7 at t. S6 (t 6 -t 7 ): At t 6, the R vrd VCI # reduces back t Ω. Thus the utput drect current sharng rat becmes.::.. S7 (t 7 -t 8 ): At t 7, the R vrq VCI # reduces back t Ω. Hence the drect current sharng rat becmes.7:.7:. S8 (t 8 -t 9 ): The R vrd rat changes rm :.: t :: at t 8. S9 (t 9 -t ): The R vrq rat changes rm ::.7 t :: at t 9. Therere, the utput drect and quadrature currents three VCIs are equal agan. The prpsed cntrller successully regulates the utput currents paralleled VCIs t the desred value. As can be bserved, even wth derent pwer rates, the VCI unts wth the prpsed cntrl strategy wll stll mantan stable peratn and acheve the nlne sharng rat change. The prpsed cntrller presents large stablty margn t the cntrl varables R vrd and R vrq. In summary, the expermental results reveal that the prpsed cntrl strategy des apply t lw-vltage parallel-vci-based system where the lne mpedance usually presents hgh rat R/X and shrt length because ts aster respnse speed, nlne sharng rat change unctn, larger stablty margn, smaller versht, plug n play peratn and decuplng cntrl. In addtn, the prpsed cntrl strategy als wrks well wth nductve-resstve lne mpedance and small purely nductve lne mpedance by means vrtual (a)

16 TPEL-Reg (b) (c) Fg. 7. Transent respnses DG, DG, and DG3 wth derent sharng rat. (a) Instantaneus utput currents DG-3, (b) Drect and quadrature utput currents DG-3, (c) Frequency DG-3. resstr. The prpsed Id V and Iq ω drp characterstcs wll present nn-lnear when the lne mpedance ver the lmtatns. Thus, the drp cntrl strategy shuld be appled t the hgh nductve system. In ther cases, the prpsed cntrl strategy can prvde superr perrmances. The prmnent eatures the prpsed strategy cmpared wth the cnventnal drp cntrl are summarzed n Table II. VII. CONCLUSION AND FUTURE WORK A smpler and aster cntrller that cmprses a PLL, a vrtual resstance lp and a PR cntrller n nner vltage lp r cntrllng drect and quadrature lad currents separately amng parallel three-phase nverters s develped. Based n the steady state characterstc analyss, by adjustng the d-axs vrtual resstance rat between the parallel nverters, the drect lad current sharng can be acheved. Whereas by mdyng the q-axs vrtual resstance rat between parallel nverters, the quadrature lad current prvded wll be changed prprtnally. The prpsed cntrl strategy des apply t lw-vltage mcrgrds and slanded mngrds. In addtn, t can als wrks well wth nductve-resstve lne mpedance and even small purely nductve r resstve lne mpedance thanks t the use vrtual resstance. Cmpared wth cnventnal drp cntrl, the descrbed methd des nt need t calculate actve and reactve pwers. Thus, the methd exhbts aster transent respnse and better precsn. Expermental results are ncluded t shw the excellent behavur the prpsed cntrller. The small sgnal mdel and stablty analyss wll be presented n Part II ths paper. APPENDIX The detaled dervatve prcess () n Sectn IV s shwn as llws. As ndcated n Fg., the clsed lp ncludes three-leg three-phase nverter, L -C lter, lne mpedance, nner vltage and current cntrl, and vrtual resstance lp. The blck dagram the nner current and vltage lps as well as the LC lter s shwn n Fg. A.. Based n the dagram, the clsed-lp transer unctn can be wrtten as llws: ' v( s) = G( s) vre ( s) Z( s) ( s) (A.) beng Gv() s G() s KPWM Gs () = LCs + ( rc + G() skpwmc )s+ + Gv() sg() skpwm (A.)

17 TPEL-Reg Cntrl capablty Transent respnse Cntrl perrmance P-V/Q- drp Yes TABLE II PERFORMANCE COMPARISON Resstve-nductve lne Purely nductve lne mpedance mpedance Prpsed cntrl Yes, but cannt wrk wth large nductve lne mpedance P-V/Q- drp Yes Prpsed cntrl Yes Zer r resstve lne mpedance P-V/Q- drp N, need change t P-/Q-V drp Prpsed cntrl Slw ast Slw ast Slw ast Gd Gd, but cannt wrk wth large nductve lne mpedance Oscllatns Gd Gd ( wth P-/Q-V drp) Yes Very well Rbustness Pr Gd Pr Gd Pr Gd Cntrl parameters m, n, Z vr R vrd, R vrq m, n, Z vr R vrd, R vrq m, n, Z vr R vrd, R vrq ' v re L Gv () s G () s KPWM I L s+ r Cs v Fg. A. Blck dagram the dual-lp cntrl sl + r Z() s = LCs rc G sk C G sg sk + ( + ( ) PWM )s+ + v( ) ( ) PWM K s v v() = pv + s + ωc G s K (A.3) (A.) G() s = Kp (A.) where G(s) presents the trackng perrmance the utput vltage llwng the vltage reerence, Z() s s the equvalent utput mpedance the nverter, v () s s the utput ' vltage, vre () s s the reerence vltage nner vltage lp, () s s the utput current, Gv () s s the PR vltage cntrl lp, G () s s the prprtnal current cntrl lp, K PWM s the gan three phase nverter, L, C and r are the nductr, capactr, and nductr ESR the LC lter respectvely, K pv and K v are the prprtnal and ntegral cecents vltage cntrl lp, ω c s the resnant requency the PR regulatr n vltage cntrl lp, and K p s the prprtnal cecents current cntrl lp. T btan the drect and quadrature lad currents, the equvalent parallel cnnected resstve-nductve lad can be represented as llws: G Lequ () Lequ Lequ s = R + sl (A.6) where GLequ() s s the equvalent lad admttance, R Lequ s the equvalent resstr, and L Lequ s the equvalent nductance. The lne mpedance can be expressed as llws: Z () s = R + sl (A.7) lne lne lne where Zlne() s s the lne mpedance, R lne s the lne resstr, and L lne s the lne nductance. Hence, the clsed lp transer unctn T plant (s) can be derved based n Fg.. v () () () () s Gs + GLequ szlne s Tplant () s = = v () s + G () s Z () s + G () s G() s + G () s Z ( s) re Lequ lne vr Lequ R R vrd beng Gvr( s) = + R sl Lequ vrq Lequ (A.8) REFERENCES [] Lasseter, R.H., "McrGrds," Pwer Engneerng Scety Wnter Meetng,. IEEE, vl., n., pp.3,-38, [] Guerrer, J.M.; Chandrkar, M.; Lee, T.; Lh, P.C., "Advanced Cntrl Archtectures r Intellgent Mcrgrds Part I: Decentralzed and Herarchcal Cntrl," Industral Electrncs, IEEE Transactns n, vl.6, n., pp.,6, Aprl 3 [3] Pag, P., Lasseter, R.H., "Autnmus cntrl mcrgrds," Pwer Engneerng Scety General Meetng, 6. IEEE, vl., n., pp., 6 [] Yunwe L, Vlathgamuwa, D.M., Ph Chang Lh, "Desgn, Analyss, and Real-Tme Testng a Cntrller r Multbus Mcrgrd System," IEEE Transactns n Pwer Electrncs, vl. 9, n., pp. 9, Sept.. [] Guerrer, J.M., Garca De Vcuna, L., Matas, J., Castlla, M., Mret, J., "Output Impedance Desgn Parallel-Cnnected UPS Inverters Wth Wreless Lad-Sharng Cntrl," IEEE Transactns n Industral Electrncs, vl., n., 63, Aug.. [6] Vasquez, J.C., Guerrer, J.M., Luna, A., Rdrguez, P., "Adaptve Drp Cntrl Appled t Vltage-Surce Inverters Operatng n Grd-Cnnected and Islanded Mdes," Industral Electrncs, IEEE Transactns n, vl. 6, n., 8896, Oct. 9. [7] Jaehng Km, Guerrer, J.M., Rdrguez, P., Tedrescu, R., Kwanghee Nam, "Mde Adaptve Drp Cntrl Wth Vrtual Output

18 TPEL-Reg Impedances r an Inverter-Based Flexble AC Mcrgrd," Pwer Electrncs, IEEE Transactns n, vl. 6, n. 3, pp , March.. [8] R. H. Lasseter and P. Pag, Mcrgrd: A cnceptual slutn, n Prc. IEEE PESC, Aachen, Germany,, pp. 89. [9] M. Marwal, J.-W. Jung, and A. Keyhan, Cntrl dstrbuted generatn systems Part II: Lad sharng cntrl, IEEE Trans. Pwer Electrn., vl. 9, n. 6, pp. 6, Nv.. [] F. Katrae and M. R. Iravan, Pwer management strateges r a mcrgrd wth multple dstrbuted generatn unts, IEEE Trans. Pwer Syst., vl., n., pp. 8 83, Nv. 6. [] Chandrkar, M.C., Dvan, D.M., Adapa, R., "Cntrl parallel cnnected nverters n standalne AC supply systems," Industry Applcatns, IEEE Transactns n, vl.9, n., pp.36,3, Jan/Feb 993 [] J. Guerrer, L. de Vcuna, J. Matas, M. Castlla, and J. Mret, A wreless cntrller t enhsance dynamc perrmance parallel nverters n dstrbuted generatn system, IEEE Trans. Pwer Electrn., vl. 9, n., pp. 3, Sep.. [3] Ashaban, S.M.; Mhamed, Y.A.-R.I. "New Famly Mcrgrd Cntrl and Management Strateges n Smart Dstrbutn Grds Analyss, Cmparsn and Testng", Pwer Systems, IEEE Transactns n, On page(s): 7-69 Vlume: 9, Issue:, Sept. [] C. Sa, P. Lehn, "Autnmus lad sharng vltage surce cnverters," IEEE Trans. Pwer Del., vl., n., pp. 9 6, Apr.. [] Yasser Abdel-Rady Ibrahm Mhamed, Ehab F. El-Saadany. "Adaptve Decentralzed Drp Cntrller t Preserve Pwer Sharng Stablty Paralleled Inverters n Dstrbuted Generatn Mcrgrds," IEEE Transactns n Pwer Electrncs, vl. 3, n. 6, pp.86-86, Nv. 8 [6] Yajuan Guan, Weyang Wu, Xaqang Gu, Herng Gu. "An Imprved Drp Cntrller r Grd-Cnnected Vltage Surce Inverter n Mcrgrd." nd Internatnal Sympsum n Pwer Electrncs r Dstrbuted Generatn Systems, PEDG, : [7] S. J. Chang, C. Y. Yen, and K. T. Chang, A multmdule parallelable seres-cnnected PWM vltage regulatr, IEEE Trans. Ind. Electrn., vl. 8, n. 3, pp. 6 6, Jun.. [8] Y. W. L, C. N. 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[8] Majumder, R., Chaudhur, B., Ghsh, A., Majumder, R., Ledwch, G., Zare, F., "Imprvement Stablty and Lad Sharng n an Autnmus Mcrgrd Usng Supplementary Drp Cntrl Lp," Pwer Systems, IEEE Transactns n, vl., n., , May.. [9] Lee, C-.T., Chu, C-.C., Cheng, P-.T., "A New Drp Cntrl Methd r the Autnmus Operatn Dstrbuted Energy Resurce Interace Cnverters," Pwer Electrncs, IEEE Transactns n, vl. 8, n., 98993, Aprl. 3. [3] Vandrn, T.L., Meersman, B.; Degrte, L., Renders, B., Vandevelde, L., "A Cntrl Strategy r Islanded Mcrgrds Wth DC-Lnk Vltage Cntrl," Pwer Delvery, IEEE Transactns n, vl.6, n., pp.73,-73, Aprl Apr.. [3] Celh, E.A.A., Crtz, P.C., Garca, P.F.D., "Small-sgnal stablty r parallel-cnnected nverters n stand-alne AC supply systems," Industry Applcatns, IEEE Transactns n, vl.38, n., pp.33,, Mar/Apr.. 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19 TPEL-Reg Lp r Grd Synchrnzatn Pwer Cnverters Under Dstrted Grd Cndtns," Industral Electrncs, IEEE Transactns n, vl.8, n., pp.738, Jan. [] Se-Ky Chung, "A Phase Trackng System r Three Phase Utlty Interace Inverters," Pwer Electrncs, IEEE Transactns n, vl., n.3, pp.338, May.. [6] Gu, X., Lu, W., Zhang, X., Sun, X., Lu, Z., Guerrer, J.M., "Flexble Cntrl Strategy r Grd-Cnnected Inverter Under Unbalanced Grd Faults Wthut PLL," Pwer Electrncs, IEEE Transactns n, vl.3, n., pp , Aprl [7] Jsep M. Guerrer, Jsé Matas, Lus García de Vcuña, Mguel Castlla, Jaume Mret, "Wreless-Cntrl Strategy r Parallel Operatn Dstrbuted-Generatn Inverters," Industral Electrncs, IEEE Transactns n, vl.3, n., pp.67, Oct. 6. Yajuan Guan (S ) receved the B.S. degree and M.S. degree n Electrcal Engneerng rm the Yanshan Unversty, Qnhuangda, Hebe, Chna, n 7 and respectvely. Frm t, she was an Assstant Pressr n Insttute Electrcal Engneerng (IEE), Chnese Academy Scences (CAS). Snce 3, she has been a Lecturer n IEE; CAS. She s currently wrkng tward her Ph.D. degree at the Department Energy Technlgy, Aalbrg Unversty, Denmark, as part the Denmark Mcrgrds Research Prgramme ( Her research nterests nclude mcrgrds, dstrbutedd generatn systems, pwer cnverter r renewable energy generatn systems, and ancllary servces r mcrgrds. Jsep M. Guerrer (S -M -SM 8-FM ) receved the B.S. degree n telecmmuncatns engneerng, the M.S. degree n electrncs engneerng, and the Ph.D. degree n pwer electrncs rm the Techncal Unversty Catalna, Barcelna, n 997, and 3, respectvely. Snce, he has been a Full Pressr wth the Department Energy Technlgy, Aalbrg Unversty, Denmark, where he s respnsblee r the Mcrgrd Research Prgram. Frm he s a guest Pressr at the Chnese Academy Scence and the Nanjng Unversty Aernautcs and Astrnautcs; rm he s char Pressr n Shandng Unversty; and rm he s a dstngushed guest Pressr n Hunann Unversty. Hs research nterests s rented t derent mcrgrd aspects, ncludng pwer electrncs, dstrbuted energy-strage systems, herarchcal and cperatve cntrl, energy management systems, and ptmzatn mcrgrds and slanded mngrds. Pr. Guerrer s an Asscate Edtr r the IEEE TRANSACTIONS ON POWER ELECTRONICS, the IEEE TRANSACTIONS ON INDUSTRIAL ELECTRONICS, and the IEEE Industral Electrncs Magazne, and an Edtr r the IEEE TRANSACTIONS n SMART GRID and IEEE TRANSACTIONS n ENERGY CONVERSION. He has been Guest Edtr the IEEE TRANSACTIONS ON POWER ELECTRONICS Specal Issues: Pwer Electrncs r Wnd Energy Cnversn and Pwer Electrncs r Mcrgrds; the IEEE TRANSACTIONS ON INDUSTRIAL ELECTRONICS Specal Sectns: Unnterruptble Pwer Supples systems, Renewable Energy Systems, Dstrbuted Generatn and Mcrgrds, and Industral Applcatns and Implementatn Issues the Kalman Flter; and the IEEE TRANSACTIONS n SMART GRID Specal Issue n Smart DC Dstrbutn Systems. He was the char the Renewable Energy Systems Techncal Cmmttee the IEEE Industral Electrncs Scety. In he was awarded by Thmsn Reuters as Hghly Cted Researcher, and n he was elevated as IEEE Fellw r hs cntrbutns n dstrbuted pwer systems and mcrgrds. Xn Zha receved the B.S. and M.S. degree n Pwer Electrncs & Electrcal Drves rm Nrthwestern Plytechncal Unversty, X an, Chna, n and 3, respectvely. He s currently wrkng tward the Ph.D. degree at Department Energy Technlgy, Aalbrg Unversty, Denmark. Hs research nterests nclude cntrl pwer cnverters, pwer qualty and mcrgrds. Juan C. Vasquez (M -SM ) receved the B.S. degree n electrncs engneerng rm the Autnmus Unversty Manzales, Manzales, Clmba, and the t Ph.D. degree n autmatc cntrl, rbtcs, and cmputer vsn rm the Techncal Unversty Catalna, Barcelna, Span, n and 9, respectvely. He was wth the Autnmus Unversty Manzales, where he taught curses n dgtal crcuts, serv systems, and lexble manuacturng systems. He was als wth the Techncal Unversty Catalna, as a Pst-Dctral Assstant, teachng curses based n renewable energy systems. In, he was Assstant Pressr n mcrgrds and currently he s wrkng as an Asscate Pressr at the Department Energy Technlgy, Aalbrg Unversty, Denmark. Dr. Vasquez s the c-respnsble the Research Prgram n Mcrgrds. Frm Feb. t Aprl. he was a Vstng Schlar at the t Center Pwer Electrncs Systems (CPES) at Vrgna Tech. Hs current research nterests nclude peratn, pwer management, herarchcal cntrl, ptmzatn and pwer qualty appled t dstrbuted generatn and ac/dc mcrgrds. Dr. Vasquez s currently a member the IEC System Evaluatn Grup SEG n LVDC Dstrbutn and Saety r use n Develped and Develpng Ecnmes and the Renewable Energy Systems Techncal Cmmttee TC-RES n IEEE Industral Electrncs Scety. Xaqang Gu (M' -SM' ) receved the B.S. and Ph.D. degrees n electrcal engneerng rm Yanshan Unversty, Qnhuangda, Chna, n 3 and 9, respectvely. He has been a Pstdctral Fellw wth the Labratry r Electrcal Drve Applcatns and Research (LEDAR), Ryersn Unversty, Trnt, ON, Canada. He s currently an asscate pressr wth the Department Electrcal Engneerng, Yanshan Unversty, Chna. He has authred/cauthredd mre than ty techncal papers, n addtn t nne patents. Hs current research nterests nclude hgh-pwer cnverters and ac drves, electrc vehcle chargng statn, and renewable energy pwer cnversn systems. Dr. Gu s a Senr Member the IEEE Pwer Electrncs Scety and IEEE Industral Electrncs Scety. He s an actve Reeree r IEEE Transactns n Sustanable Energy, IEEE Transactns n Smart Grd, IEEE Transactns n Industral Electrncs and IEEE Transactnss n Pwer Electrncs.