A Stable Control Strategy for Input-Series Output- Series Connected Boost half Bridge DC-DC Converter

Transcription

1 TELKOMNIK Indnesan Jurnal f Electrcal Engneerng l., N., January 04, pp. 7 ~ 79 DOI: 7 Stable Cntrl Strategy fr Input-Seres Output- Seres Cnnected Bst half Brdge DC-DC Cnerter mr Mahmd Smr*, mjad l Syed, Shahnawaz Farhan Khahr 3, La Xazhng 4, Farhan Manzr 5, 3, 4, 5 Schl f utmatn, Bejng Insttute f Technlgy, Bejng 0008, Chna Schl f Mechatrncal Engneerng, Bejng Insttute f Technlgy, Bejng0008, Chna, Mehran Unersty f Engneerng and Technlgy, Jamshr, Sndh, Pakstan *Crespndng authr, e-mal: aamr.m.smr@gmal.cm bstract Bst half brdge DC-DC cnerters n the cmbnatn f an nput-seres and utput-seres (ISOS) cnnected cnfguratn wth a stable cntrl strategy has been nestgated n ths paper. stable cntrl strategy cmprses f tw lps that are current lp and ltage lp. The reference t the current lp has been chsen frm the nput sde f the DC-DC cnerter. The reference t the ltage lp has been selected frm the utput sde f the DC-DC cnerter. Such a reference makes the crcut cnfguratn smple, easy and eentually results n reduced cst. The cntrl strategy fr nput-seres utput-seres (ISOS) cnfguratn f DC-DC cnerters s prpsed t achee equal nput ltage sharng (IS) as well utput ltage sharng (OS). Furthermre, n ths paper, the perfrmance f the stable cntrl strategy fr nput-seres utput-seres (ISOS) bst half brdge DC-DC cnerter has been bsered nt nly fr the fxed but als fr the aryng and cntnuusly aryng lad. The prpsed Stable cntrl scheme has been deelped by mdelng t n MTLB usng Smulnk and Smpwer tlbxes. The peratn f the prpsed stable cntrl strategy has been fund t be satsfactry. Keywrds: Bst half brdge (BHB) DC-DC Cnerter, Input current sharng (ICS), Input-seres Outputseres (ISOS), Input ltage sharng (IS), Output current sharng (OCS), Output ltage sharng (OS). Cpyrght 04 Insttute f danced Engneerng and Scence. ll rghts resered.. Intrductn T realze any nput-utput specfcatns f bst half brdge DC-DC cnerters n pwer system archtecture ether n seres r parallelcan be cnnected n any cmbnatn bth at the nput as well as at the utputsdes []. Input-utput cmbnatns can pssbly be cnnected n fur dfferent frm [], [3]. Presently ne f them s qute well knwn due t ts many applcatns, the nput-parallel, utput-seres (IPOS) cnnectn; requrng hgh utput ltages [3]. The applcatns requrng lw-ltage and hgh current utputs uses nput parallel, utput-parallel (IPOP) cmbnatn. Input seres utput seres (ISOS) cnerters allw apprprate cntrl technques s as t cnnect n seres fr dynamc ltage sharng capablty at the nput. It has seeral merts fr example utlzatn f lwer ltage MOSFETs [4], [5] and mpred transent perfrmance. Ths paper ntrduces a stable cntrl strategy cnsstng f tw lps fr ISOS cnfguratn, related t that f ISOP cnfguratn [6], [7], t make sure that nput-ltage and utput-ltage dstrbutn amngst the cnerters s shared equally. The ISOS cnfguratn s cmpatble n applcatns where hgh nput ltage and utput ltage s requred mutually. [], [8]. Multleel cnerters hae an adantage f usng lw-ltage ratng swtches fr hgh ltage applcatns. Neertheless, fr a large number f ddes r capactrs, system relablty cannt be assured [9]. Bth the nput and utput f the ISOS cnfguratn cntans seeral DC- DC cnerters cnnected n seres cmbnatn. Ths enables a utlzatn f lw ltage ratng MOSFETs wth hgh swtchng frequency, whch leads tward hgh cnersn effcency [7]. Hweer, cntrl must be taken t make sure equal nput ltage dstrbutn amng all f the mdules fr the ISOS DC-DC cnerters. small number f cntrl schemes t achee ths purpsehae been prpsed [0]. One f them was prpsed wth nput ltage and utput ltage lp and the ther was prpsed wth an addtnal current lp wth nput and utput ltage lps [], [6]. Hweer, bth nput ltages and nput currents hae been sensed. Receed May 4, 03; Resed ugust, 03; ccepted September 9, 03

2 73 ISSN: TELKOMNIK Three-lp cntrl strategy [] was appled by means f sensng bth nput ltages and utput currents []. The dsadantages f the frmer cntrl strategy are pr dynamc respnse and lacks f resstance t lad shrt crcutng. lthugh usng the latter cntrl strategy these dsadantages can be ercme by usng nner current trackng lps. It s mre cmplex [0] and nt cst effecte. Therefre, ths paper prpses a ery smple IS and OS cntrl fr ISOS bst half brdge DC-DC cnerter systems, whch des nt requre changng the ltage references fr each cnerter. Perfect ltage sharng can be acheed by frcng the nput ltage between the cnerters equally, n matter what the ttal nput ltage s. The prpsed nddual cnerters cnsst f bst half brdge DC-DC cnerters, whch hae the adantages f n rsks f shtng thrugh, autmatc ltage spke clampng and demagnetzng thrugh ddes [7]. Ths paper s structured as fllws. The Input seres utput seres mechansm s dscussed n sectn II alng wth the mathematcal representatn. The prpsed stable cntrl strategy s presented n Sectn III. Smulatn and results are llustrated n Sectn I. Representatn f results n blck dagram has been demnstrated n sectn. Cnclusns are gen n Sectn I.. Input Seres and Output-Seres Cnfguratn (ISOS).. Crcut Descrptn Tw mdules cmprsng f bst half brdge DC-DC cnerter are cnnected n seres at the nput and utput sde as shwn n fgure whch s represented as the general blck dagram f ISOS cnfguratn. Fgure. Blck dagram f ISOS BHB DC-DC Cnerter s shwn n fgure, the ISOS BHB DC-DC cnerter cnfguratn cnsdered here cnssts f a DC ltage surce n, feedng tw bst half brdge DC-DC cnerters. Each BHB DC-DC cnerter cnssts f nput nductance and half brdge at the nput sde f the hgh frequency transfrmer whereas ltage dubler rectfer s cnnected at utput f the hgh frequency transfrmer. Fgure als descrbes the feasblty f the prpsed ISOS system, under steady state usng the dea f pwer balancen presence f aryng and cntnuusly aryng lad. Under steady state cndtn tw cnerters can hae equal aerage nput currents caused by the seres cmbnatn at the nput. In the same way, under steady state cndtn tw cnerters can hae the equal aerage utput currents caused by the seres cmbnatn at the utput. Furthermre f the tw cnerters mantan ther nput ltages equally by cntrl strategy, subsequently nput pwers, and as a result, by means f pwer balance, the utput pwers f the tw cnerters wll be the same. Hence ths descrbes that tw cnerters autmatcally share the utput ltage equalently. The slated hgh frequency transfrmers hang the turns rat f : N, where the N s equal t. Equal duty rats can be generated fr the tw cnerters wth the help f cntrl TELKOMNIK l., N., January 04: 7 79

3 ISSN: strategy because the cnerters are dentcal. The cnfguratn f ISOS bst half brdge DC- DC cnerter s nt nly made fr the fxed but als fr aryng and cntnuusly aryng lad, nspte f whch the nput and utput f the cnerters share equal ltages. Ths apples t cnerters wrkng under current mde cntrl plus ltage mde cntrl, besdes t can furthermre be expanded t seeral number f cnerters cnnected n seres. n Fgure. Schematc dagram f ISOS BHB DC-DC Cnerter.. Mathematcal Representatn Fgure shws schematc f ISOS cnerter made up f tw bst half brdge DC-DC cnerters. The ttal nput ltage n s dded nt n and n acrss each cnerter mdule respectely. Thus we get the ltages fr each cnerter mdule wrkng as nddual nput. Hence ttal nput ltage n, descrbed as Input ltage sharng (IS) fr tw bst half brdge DC-DC cnerters fr ISOS cnfguratn and can be descrbe as: () n n n The tw cnerter mdules are cnsdered t be dentcal, therefre t s bus that the nput ltage sharng (IS) fr tw bst half brdge DC-DC cnerters can be represented as: () n n Hweer, satsfyng () s ur basc cntrl bjecte. Ths bjecte has nt nly been cnsdered fr the fxed but als fr aryng and cntnuusly aryng lad. Once the ltage acrss the nput sde s equal cnsequently the ltage acrss the utput wll be equal. Hence the ltage sharng between the nput and utput can be btaned. 3. Prpsed Stable Cntrl Strategy The cntrl strategy f cnentnal DC-DC cnerter s desgned n a sphstcated way. The prpsed stable cntrl strategy fr ISOS BHB DC-DC cnerter s llustrated n Fgure 3. Stable Cntrl Strategy fr Input-Seres Output-Seres Cnnected Bst half... (mr MS)

4 75 ISSN: TELKOMNIK ref ref n Q ~ Q n n ref ref n Q ~ Q 3 4 n n Fgure 3. Prpsed Stable Cntrl Strategy Prpsed stable cntrl strategy cntans tw lps that are ltage lp and current lp. Cnsequently wth the help f abe sad lps the cntrlblck can achee equal IS and equal OS smultaneusly 4. Smulatns and Results The tw bst half brdge DC-DC cnerters wth ISOS cnfguratn was smulated alng wth prpsed stable cntrl strategy. The specfcatns fr the smulated mdel are represented n Table. In rder t shw effcent perfrmance f prpsed stable cntrl strategy fr ISOS cnfguratn f the tw cnerters was nt nly smulated fr fxed but als fr aryng and cntnuusly aryng lad. Therefre the smulatn results are classfed nt three dfferent sectns. Table. Specfcatns Parameters alue Parameters alue Input ltage 50 Output ltage 00 Input Inductance 00µH Output capactance 8µF Input Capactance 0µF Fxed lad 50 Ohms Swtchng frequency 0KHz aryng lad 5-50 Ohms 4. Smulatn Results fr Fxed Lad Fgure 4, n general, s representng the equal utput ltage sharng (OS), nput current sharng and utput current sharng, and the lad ltage. Fgure 4 s classfed frm 4. t 4.4. Fgure 4. s representng the nput current, fgure 4. shws the utput current, fgure 4.3 ndcates utput ltage sharng (OS) n each mdule respectely and fgure 4.4 llustrates the lad ltage. 4. Smulatn Results fr aryng Lad The smulatn results fr aryng lad are shwn n Fgure 5. When lad s aryng the nput current alues change frm 4 t 8 and cnsequently the alues f utput currents als change but the ltages reman cnstant. Fgure 5 s classfed frm 5. t 5.4. Fgure 5. s representng the nput current, Fgure 5. shws the utput current, Fgure 5.3 ndcates utput ltage sharng (OS) n each mdule respectely and Fgure 5.4 llustrates the lad ltage. TELKOMNIK l., N., January 04: 7 79

5 ISSN: n n L 00 Fgure 4. Representng the equal utput ltage sharng (OS), nput current sharng and utput current sharng, and the lad ltage n n 8 n n 8 L L Fgure 5. The smulatn results fr aryng lad are shwn 4.3. Smulatn Results fr Cntnuusly aryng Lad The smulatn results descrbed n Fgure 6 llustrate the cntnuus lad aratn due t whch the nput current ares frm 8 (half f the full lad) t 4 (full lad) and agan ges t Stable Cntrl Strategy fr Input-Seres Output-Seres Cnnected Bst half... (mr MS)

6 77 ISSN: TELKOMNIK 8, as the result the utput current changes accrdngly, but the ltages reman cnstant. Fgure 6 s classfed frm 6. t 6.4. Fgure 6. s representng the nput current, Fgure 6. shws the utput current, Fgure 6.3 ndcates utputltage sharng (OS) n each mdule respectely and Fgure 6.4 llustrates the lad ltage. 8 n 8 n 4 n 4 n 8 n 8 n 4 50 L L L 00 Fgure 6. Ilustratng f the cntnuus lad aratn 5. Representatn f Results The results f ISOS BHB DC-DC cnerter cnfguratn btaned abe can be demnstrated belw by cnsderng the blck dagram f Fgure. s descrbed n Table. the lad can be ared by 5Ω (half f the full lad) t 50Ω (full lad), therefre Fgure 7 shws the blck f ISOS cnfguratn wth results at full lad (R L =50Ω) and Fgure 8 ndcates the blck dagram f ISOS cnfguratn wth results at half lad (R L =5Ω). n n n 5 n n L 00 n 5 Fgure 7. Blck dagram f ISOS cnfguratn wth results at full lad (R L =50Ω) TELKOMNIK l., N., January 04: 7 79

7 ISSN: n 8 8 n n 5 n n 8 L 00 n 5 Fgure 8. Blck dagram f ISOS cnfguratn wth results at half lad (R L =5Ω) 6. Cnclusn stable cntrl strategy alng wth the cnfguratn f ISOS cnnectn f bst half brdge DC-DC cnerters prpsed here descrbed that under steady state cndtnequal IS and OS can be btaned. The prpsed Stable cntrlscheme s erfed fr fxed lad, aryng lad and cntnuusly aryng lad fr the ISOS cnnected bst half brdge DC-DC cnerters. Prprtnal Integral cntrller wth PWM s enugh fr the current lp and ltage lp t mantan the IS and OS equally. The stable cntrl strategy has been cnfrmed thrugh smulatn and results are presented. lthugh tw cnerters system has been cncentrated n ths paper, the desgn and analyss technques are applcable fr any number f seres cnnected cnerters References [] R Gr, R yyanar and Enrque Ledezma. Input-Seres and Output-Seres Cnnected Mdular DC-DC Cnerters wth cte Input ltage and Output ltage Sharng. IEEE Prceesdngs. 004; [] W Chen, X Ruan, H Yan, and CK Tse. DC-DC cnersn systems cnsstng f multple cnerter mdules: stablty, cntrl, and expermental erfcatns. IEEE Trans. Pwer Electrn. 009; 4(6): [3] SN Manas, G Kstaks. Mdular DC-DC cnertr fr hgh-utput ltage applcatns. IEE Prceedngs B Electrc Pwer pplcatns. 993; 40(): [4] jay Chudhary, Enrque Ledezma, Raja yyanar, and Rbert M Buttn. Fault Tlerant Crcut Tplgy and Cntrl Methd fr Input-Seres and Output-Parallel Mdular DC-DC Cnerters. IEEE Transactns n Pwer Electrncs. 008; 3(). [5] JW Km, JS Yu, and BH Ch. Mdelng, cntrl and desgn f nput-seres-utput-parallel-cnnected cnerter fr hgh-speed-tran pwer system. IEEE Trans. Ind. Electrn. 00; 48(3): [6] R yyanar, R Gr, N Mhan. cte nput-ltage and lad-current sharng n nput-seres and utput parallel cnnected mdular DC-DC cnerters usng dynamc nput-ltage reference scheme. IEEE Trans. Pwer Electrncs [7] Deshang Sha, Zhqang Gu, and Xazhng La. Dgtal Cntrl Strategy fr Input-Seres-Output- Parallel Mdular DC-DC Cnerters. Jurnal f Pwer Electrncs. 00; 0(3): [8] S Inue and H kag. bdrectnal slated dc dc cnerter as a cre crcut f the next-generatn medum-ltage pwer cnersn system. IEEE Trans. Pwer Electrn. 007; (): [9] FH Khan, et al. multleel mdular capactr clamped DC DC cnerter. IEEE Trans. Ind. ppl. 007; 43(6): [0] Deshang Sha, Zhqang Gu, and Xazhng La. Crss-Feedback Output-Current-Sharng Cntrl fr Input-Seres-Output-Parallel Mdular DC DC Cnerters. IEEE Transactns n Pwer Electrncs. 00; 5(): [] X Ruan, W Chen, L Cheng, CK Tse, H Yan, and T Zhang. Cntrl strategy fr nput-seres- utputparallel cnerters. IEEE Trans. Ind.Electrn. 009; 56(4): [] W Chen, K Zhuang, and X Ruan. nput-seres- and utput-parallel cnnected nerter system fr hgh-nput-ltage applcatns. IEEE Trans. Pwer Electrn. 009; 4(9): [3] mr Mahmd Smr, Xulng Yu, Shahnawaz Farhan Khahr, La Xazhng. Hgh utput ltage based multphase step up DC-DC cnerter tplgy wth ltage dubler rectfers. Telkmnka Indnesan Jurnal f Electrcal Engneerng. 03; (): Stable Cntrl Strategy fr Input-Seres Output-Seres Cnnected Bst half... (mr MS)

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