A DRAM based Physical Unclonable Function Capable of Generating >10 32 Challenge Response Pairs per 1Kbit Array for Secure Chip Authentication

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1 A DRAM based Physical Unclonable Function Capable of Generating >10 32 Challenge Response Pairs per 1Kbit Array for Secure Chip Authentication Q. Tang, C. Zhou, *W. Choi, *G. Kang, *J. Park, K. K. Parhi, and C. H. Kim University of Minnesota, Minneapolis, USA *Korea University, Seoul, Korea

2 Agenda Background Proposed DRAM based Strong PUF Enhancing DRAM PUF Uniqueness and Stability Hamming Distance Measurements Summary 1

3 Agenda Background Proposed DRAM based Strong PUF Enhancing DRAM PUF Uniqueness and Stability Hamming Distance Measurements Summary 2

4 Physical Unclonable Function (PUF) Fingerprint of chip PUF Inputs Challenge #1 Challenge #2 Numerous input choices Outputs Response #1 Response #2 Challenge #n Response #n Unique and random: Based on inherent process variation Secure: Large # of challenge-response pairs (CRPs) Unique and random responses Challenges Chip #1 Chip #2 Responses #1 Responses #2 4 5

5 Weak PUF vs. Strong PUF Weak PUF: # of CRPs* proportional to # of unit cells Example: SRAM PUF Application: key generation BL WL WL BLB Strong PUF: # of CRPs exponential to # of unit stages (2 n ) Example: MUX arbiter PUF Application: system authentication #1 #n Response S Q SR Latch R Challenge *CRP: Challenge Response Pair 5

6 DRAM Retention Characteristics WL t refresh BL Leakage V storage Vstorage Time Vref Data retention time depends on the leakage current and capacitance of the storage node Refresh required before the cell data flips 3

7 DRAM based PUF Write All 1 s Retention Failure Map Wait > 40μs Data 1 Data 0 Failure locations unique to each chip Retention time adjusted by word line voltage Only weak PUF configuration implemented S. Rosenblatt, et al., JSSC, 2013 (IBM) 4

8 SRAM PUF vs. DRAM PUF SRAM PUF DRAM PUF Schematic WL WL WL Vstorage BL BLB BL Challenge Method Power up VDD Response value = 0 or 1 Vstorage Write '1' Vref Write '0' t wait Time Time Key Features Power off required Weak PUF configuration only Power is kept on Strong PUF configuration possible V, T variation can be compensated 6

9 Agenda Background Proposed DRAM based Strong PUF Enhancing DRAM PUF Uniqueness and Stability Hamming Distance Measurements Summary 7

10 Proposed 2T DRAM based PUF 2T DRAM WWL (VDD+0.4V) RBL (VDD) 1T1C DRAM WL WBL (GND) V storage V storage RWL (VDD) BL K. Chun, et al., ISSCC 2011, JSSC 2012 Logic compatible Retention time similar to 1T1C t wait = 10.5ms induces 10% 27ºC 8

11 DRAM based Strong PUF Array 2T gain cell RBL SA+Writeback WBL 01 9 IO_SEL RIO WIO Column Decoder (5 bits) WWL RWL Vref Row Decoder (5 bits) Chip IOs

12 Proposed Authentication Scheme Upper Array Input Pattern (128 bits) Unused cells Flipped cells Data 1 Data 0 Step 1: Write a 128 bit pattern to selected upper array Challenge: start location (=512) + input data ( 1 or 0 ) 13

13 Proposed Authentication Scheme Upper Array Input Pattern (128 bits) After 10.5ms Hidden Pattern Unused cells Flipped cells Data 1 Data 0 Step 2: Wait for 10.5ms to induce 10% cell failures Internally generated pattern is hidden to outside world 13

14 Proposed Authentication Scheme Upper Array Input Pattern (128 bits) After 10.5ms Hidden Pattern Unused cells Flipped cells Data 1 Data to 512 Random Mapping Lower Array Step 3: Write hidden pattern to lower array Challenge: mapping information (=Permutation(512, 128)) 13

15 Proposed Authentication Scheme Upper Array Input Pattern (128 bits) After 10.5ms Hidden Pattern Unused cells Flipped cells Data 1 Data to 512 Random Mapping Lower Array After 10.5ms Final Response (128 bits) Step 4: Collect responses from lower array after 10.5ms # of Challenges = Permutation(512, 128) 13

16 Enrollment and Authentication Flow Enrollment Write 1 or 0 DRAM Array No Mask Cell stable? W 1 R? W 0 R? Yes Server 14

17 Enrollment and Authentication Flow Enrollment Write 1 or 0 Authentication Calibration DRAM Array No Mask Cell stable? W 1 R? W 0 R? Yes Server 15

18 Enrollment and Authentication Flow Enrollment Write 1 or 0 Authentication Calibration No Mask DRAM Array Cell stable? W 1 R? W 0 R? Yes Start cell address Input Pattern Write Upper Array Repetitive Read Write-backs Hidden Pattern Challenge Server 16

19 Enrollment and Authentication Flow Enrollment Write 1 or 0 Authentication Calibration No Mask DRAM Array Cell stable? W 1 R? W 0 R? Yes Challenge Start cell address Random Mapping Input Pattern Write Upper Array Repetitive Read Write-backs Hidden Pattern Write Lower Array Repetitive Read Write-backs Response Server 17

20 Agenda Background Proposed DRAM based Strong PUF Enhancing DRAM PUF Uniqueness and Stability Hamming Distance Measurements Summary 18

21 DRAM PUF Response Distribution Probability (%) Write 1 6.5% 65nm, 1.2V, 27ºC 1K memory cells, 500 trials 84.7% Average Response Stable cells (84.7%) Flipped cells (6.5%) Unstable cells (8.8%) Average response over 500 trials More flip cells (red color bar) desired Few unstable cells (gray color bar) desired 1 After 10.5 ms After 10.5 ms After 10.5 ms

22 Repetitive Write-back Scheme Stable cells Flipped cells One-time read-out Repetitive write-back The flip can happen at any time Unstable cells Weak 1 cell tends to be a strong 0 cell, and vice versa Repetitive write-back = detect flip in repeated test % of stable cells, % of flip cells, % of unstable cells 20

23 Repetitive Write-back Scheme W 1 W 0 Always % 6.5% Always 0 Unstable No write-backs 6.5% 8.8% 7.2% 10 write-backs W 1 W % 11.6% 86.3% 12.7% 83.2% 6.0% 5.2% Unstable Cells (%) nm, 1.2V, 27ºC Write # of write-backs # of flipped cells increases: better uniqueness # of unstable cells decreases: better stability 21

24 Agenda Background Proposed DRAM based Strong PUF Enhancing DRAM PUF Uniqueness and Stability Hamming Distance Measurements Summary 22

25 Intra- and Inter-chip Hamming Distance Probability (%) Intra-Chip (w/ masking) µ = , σ = , trails = 500 Inter-Chip (15 Chips,10K Challenges) µ = , σ = Margin = nm, 1.2V, 27ºC, 128 CRPs Hamming Distance Inter-chip HD avg 0.5 due to a flip ratio of 10% margin reliable authentication 23

26 Retention Map vs. Supply Voltage Desired flipping probability range: 9%<P flip <11% 24

27 Retention Map vs. Temperature Desired flipping probability range: 9%<P flip <11% 25

28 Calibration Flow Write half 1 s & half 0 s Read after t wait 1 & 0 ratio equal? Yes Flip ratio in range? Adjust V ref No Adjust t wait No Target retention failure rate: 9%~11% Calibration performed before each authentication request Start Yes 26

29 Intra-chip HD under Different V and T Probability (%) ~1.2V 1.0, 1.1V 0.9V 65nm, 27ºC Before calibration After calibration 0.8V Probability (%) ~85ºC -15ºC 65nm, 1.2V Before Calibration After Calibration 85ºC Hamming Distance (Intra-Chip) Hamming Distance (Intra-Chip) μ and σ of the intra-chip Hamming distance distribution are getting smaller after calibration 0 27

30 Summary A 2T DRAM based Strong PUF demonstrated in 65nm LP CMOS Number of CRPs > A repetitive write-back scheme proposed to enhance PUF uniqueness and stability A calibration scheme mitigates voltage and temperature effects Acknowledgement This work was supported in part by the National Science Foundation under Grant CNS , and in part by the Semiconductor Research Corporation under Contract 2014-TS

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