Security Evaluation and Enhancement of Bistable Ring PUFs
|
|
|
- Cecil Bennett
- 5 years ago
- Views:
Transcription
1 ecurity Evaluation and Enhancement of Bistable ing PUFs FIDec, June 23, 25 Xiaolin Xu (), Ulrich ührmair (2) Daniel Holcomb () and Wayne Burleson () () UMass Amherst (2) HGI, U Bochum This material is based upon work supported by: NF CN and C task Its contents are solely the responsibility of the authors and do not necessarily represent the official views of C or NF.
2 Outline Background PUFs Modeling attacks on PUFs Bistable ing PUF ecurity Evaluation of B PUFs Modeling the B PUF esults against B PUF and variants ecurity Enhancement of B PUFs XOing B PUFs to enhance the security Impact on other PUF parameters Conclusion and future work FIDsec 25 2
3 Physical Unclonable Functions Map challenges to responses according to physical variations ecurity applications include key storage and authentication Challenges f esponses FIDsec 25 3
4 Physical Unclonable Functions Map challenges to responses according to physical variations ecurity applications include key storage and authentication Challenges f esponses PUF Characterized by Challenge- esponse Pairs (CPs) Exponential challenge space Modeling attacks should not be possible FIDsec 25 3
5 PUFs and Modeling Attacks Q () D. Lim. Mc Thesis, MIT, 24 (2) U. ührmair, et al, T-IF, 23 (3) M. Majzoobi, et al. ICCAD 28 (4) U. ührmair, et al, CHE 24 (5) G. uh et al. DAC 27 (6) U. ührmair, et al, CC 2 (7) G. Becker, CHE 25 (8) chuster et al., TUT 25 FIDsec 25 4
6 PUFs and Modeling Attacks Q Challenges: Ci 2 n (n= num stages) () D. Lim. Mc Thesis, MIT, 24 (2) U. ührmair, et al, T-IF, 23 (3) M. Majzoobi, et al. ICCAD 28 (4) U. ührmair, et al, CHE 24 (5) G. uh et al. DAC 27 (6) U. ührmair, et al, CC 2 (7) G. Becker, CHE 25 (8) chuster et al., TUT 25 FIDsec 25 4
7 PUFs and Modeling Attacks Q Challenges: Ci 2 n (n= num stages) () D. Lim. Mc Thesis, MIT, 24 (2) U. ührmair, et al, T-IF, 23 (3) M. Majzoobi, et al. ICCAD 28 (4) U. ührmair, et al, CHE 24 (5) G. uh et al. DAC 27 (6) U. ührmair, et al, CC 2 (7) G. Becker, CHE 25 (8) chuster et al., TUT 25 FIDsec 25 4
8 PUFs and Modeling Attacks Q Challenges: Ci 2 n (n= num stages) esponses: ri {,} (n= shown) voltage Q= time () D. Lim. Mc Thesis, MIT, 24 (2) U. ührmair, et al, T-IF, 23 (3) M. Majzoobi, et al. ICCAD 28 (4) U. ührmair, et al, CHE 24 (5) G. uh et al. DAC 27 (6) U. ührmair, et al, CC 2 (7) G. Becker, CHE 25 (8) chuster et al., TUT 25 FIDsec 25 4
9 PUFs and Modeling Attacks Q Q= Challenges: Ci 2 n (n= num stages) esponses: ri {,} (n= shown) voltage time () D. Lim. Mc Thesis, MIT, 24 (2) U. ührmair, et al, T-IF, 23 (3) M. Majzoobi, et al. ICCAD 28 (4) U. ührmair, et al, CHE 24 (5) G. uh et al. DAC 27 (6) U. ührmair, et al, CC 2 (7) G. Becker, CHE 25 (8) chuster et al., TUT 25 FIDsec 25 4
10 PUFs and Modeling Attacks Q Challenges: Ci 2 n (n= num stages) esponses: ri {,} (n= shown) voltage Q= time () D. Lim. Mc Thesis, MIT, 24 (2) U. ührmair, et al, T-IF, 23 (3) M. Majzoobi, et al. ICCAD 28 (4) U. ührmair, et al, CHE 24 (5) G. uh et al. DAC 27 (6) U. ührmair, et al, CC 2 (7) G. Becker, CHE 25 (8) chuster et al., TUT 25 FIDsec 25 4
11 PUFs and Modeling Attacks Q Challenges: Ci 2 n (n= num stages) esponses: ri {,} (n= shown) voltage Q= time Q= voltage time () D. Lim. Mc Thesis, MIT, 24 (2) U. ührmair, et al, T-IF, 23 (3) M. Majzoobi, et al. ICCAD 28 (4) U. ührmair, et al, CHE 24 (5) G. uh et al. DAC 27 (6) U. ührmair, et al, CC 2 (7) G. Becker, CHE 25 (8) chuster et al., TUT 25 FIDsec 25 4
12 PUFs and Modeling Attacks Q Challenges: Ci 2 n (n= num stages) esponses: ri {,} (n= shown) Q= Arbiter voltage PUF susceptible to additive delay model Q= time voltage time () D. Lim. Mc Thesis, MIT, 24 (2) U. ührmair, et al, T-IF, 23 (3) M. Majzoobi, et al. ICCAD 28 (4) U. ührmair, et al, CHE 24 (5) G. uh et al. DAC 27 (6) U. ührmair, et al, CC 2 (7) G. Becker, CHE 25 (8) chuster et al., TUT 25 FIDsec 25 4
13 PUFs and Modeling Attacks Q Challenges: Ci 2 n (n= num stages) esponses: ri {,} (n= shown) Arms race of designs versus attacks ongoing. XO PUF (5), Lightweight PUF (3) voltage Q= Arbiter voltage PUF susceptible to additive delay model VM (), Evolutionary trategies (6), Logistic egression (6), ANN (8), Hybrid attacks (4) Q= time time () D. Lim. Mc Thesis, MIT, 24 (2) U. ührmair, et al, T-IF, 23 (3) M. Majzoobi, et al. ICCAD 28 (4) U. ührmair, et al, CHE 24 (5) G. uh et al. DAC 27 (6) U. ührmair, et al, CC 2 (7) G. Becker, CHE 25 (8) chuster et al., TUT 25 FIDsec 25 4
14 Bistable ing PUFs B PUF (5) is composed of n-stages, where each stage has two inverting delay elements (NO gates as an example) Each challenge vector configures a unique ring Ci 2 n (n= num stages) ing has two stable states ri {,} (5) Q Chen, et al. HOT, 2 FIDsec 25 5
15 FPGA implementation B PUF implemented on partan VI FPGA 64-bit B PUF implementation including peripheral logic, I/O etc # of slices 3556 # of slice flip flops 3688 # of LUTs gates to implement only the basic B PUF FIDsec 25 6
16 Outline Background PUFs Modeling attacks on PUFs Bistable ing PUF ecurity Evaluation of B PUFs Modeling the B PUF esults against B PUF and variants ecurity Enhancement of B PUFs XOing B PUFs to enhance the security Impact on other PUF parameters Conclusion and future work FIDsec 25 7
17 Evaluating esponse of B PUF. Apply reset and challenge to configure ring 2. elease reset 3. ead response after allow time for stabilization FIDsec 25 8
18 Evaluating esponse of B PUF. Apply reset and challenge to configure ring 2. elease reset 3. ead response after allow time for stabilization FIDsec 25 8
19 Evaluating esponse of B PUF. Apply reset and challenge to configure ring 2. elease reset 3. ead response after allow time for stabilization FIDsec 25 8
20 Evaluating esponse of B PUF. Apply reset and challenge to configure ring 2. elease reset 3. ead response after allow time for stabilization FIDsec 25 8
21 Evaluating esponse of B PUF. Apply reset and challenge to configure ring 2. elease reset 3. ead response after allow time for stabilization FIDsec 25 8
22 Modeling the B PUF epresent each stage by two weights Weights represent tendency to favor a stage output of over stage output of ti represents weight of top gate in i th stage bi represents weight of bottom gate in i th stage ti bi Assumption: there exist weights that explain the challenge response mapping of B PUF FIDsec 25 9
23 Example Challenge bits select weights, stage index determines signs esponse tells whether sum is negative or positive Additive delay model (like Arbiter PUF) t b + t 2 t 3 + b 4 b 5 + t 6 t 7 FIDsec 25
Example. Security of Bistable Ring PUF
Example Challenge bits select weights, stage index determines signs Response tells whether sum is negative or positive Additive delay model (like Arbiter PUF) t 0 b 1 + t 2 t 3 + b 4 b 5 + t 6 t 7 1 0
Bitline PUF:! Building Native Challenge-Response PUF Capability into Any SRAM. Daniel E. Holcomb Kevin Fu University of Michigan
Sept 26, 24 Cryptographic Hardware and Embedded Systems Bitline PUF:! Building Native Challenge-Response PUF Capability into Any SRAM Daniel E. Holcomb Kevin Fu University of Michigan Acknowledgment: This
Employing Process Variation for Building Chip Identifiers
Turning Lemons into Lemonade: Employing Process Variation for Building Chip Identifiers Leyla Nazhandali, Electrical and Computer Eng. Department Virginia Tech Outline Part 1: What are PUFs? Identity of
FPGA PUF Based on Programmable LUT Delays
FPGA PUF Based on Programmable LUT Delays Bilal Habib Kris Gaj Jens-Peter Kaps Cryptographic Engineering Research Group (CERG) http://cryptography.gmu.edu Department of ECE, Volgenau School of Engineering,
SRAM-based Physical Unclonable Functions
Feb 26, 25 @ Worcester Polytechnic Institute SRAM-based Physical Unclonable Functions Daniel E. Holcomb UMass Amherst Collaborators for these works: Wayne P Burleson Kevin Fu Amir Rahmati Uli Ruhrmair
Soft Response Generation and Thresholding Strategies for Linear and Feed-Forward MUX PUFs
Soft Response Generation and Thresholding Strategies for Linear and Feed-Forward MUX PUFs Chen Zhou, SarojSatapathy, YingjieLao, KeshabK. Parhiand Chris H. Kim Department of ECE University of Minnesota
Moving PUFs out of the lab
Moving PUFs out of the lab Patrick Schaumont 2/3/2012 Research results by Abhranil Maiti, Jeff Casarona, Luke McHale, Logan McDougall, Vikash Gunreddy, Michael Cantrell What is a Physical Unclonable Function?
Physical Unclonable Functions (PUFs) and Secure Processors. Srini Devadas Department of EECS and CSAIL Massachusetts Institute of Technology
Physical Unclonable Functions (PUFs) and Secure Processors Srini Devadas Department of EECS and CSAIL Massachusetts Institute of Technology 1 Security Challenges How to securely authenticate devices at
www.unique-project.eu Exchange of security-critical data Computing Device generates, stores and processes security-critical information Computing Device 2 However: Cryptographic secrets can be leaked by
Reverse Engineering and Prevention Techniques for Physical Unclonable Functions Using Side Channels
Reverse Engineering and Prevention Techniques for Physical Unclonable Functions Using Side Channels Sheng Wei * James B. Wendt * Ani Nahapetian * Miodrag Potkonjak * * University of California, Los Angeles
A DRAM based Physical Unclonable Function Capable of Generating >10 32 Challenge Response Pairs per 1Kbit Array for Secure Chip Authentication
A DRAM based Physical Unclonable Function Capable of Generating >10 32 Challenge Response Pairs per 1Kbit Array for Secure Chip Authentication Q. Tang, C. Zhou, *W. Choi, *G. Kang, *J. Park, K. K. Parhi,
Variation Aware Placement for Efficient Key Generation using Physically Unclonable Functions in Reconfigurable Systems
University of Massachusetts Amherst ScholarWorks@UMass Amherst Masters Theses Dissertations and Theses 2016 Variation Aware Placement for Efficient Key Generation using Physically Unclonable Functions
Secure and Energy Efficient Physical Unclonable Functions
University of Massachusetts Amherst ScholarWorks@UMass Amherst Masters Theses 1911 - February 2014 Dissertations and Theses 2012 Secure and Energy Efficient Physical Unclonable Functions Sudheendra Srivathsa
IMPROVING THE QUALITY OF A PHYSICAL UNCLONABLE FUNCTION USING CONFIGURABLE RING OSCILLATORS Abhranil Maiti, Patrick Schaumont
IMPROVING THE QUALITY OF A PHYSICAL UNCLONABLE FUNCTION USING CONFIGURABLE RING OSCILLATORS Abhranil Maiti, Patrick Schaumont Electrical and Computer Engineering Department Virginia Tech Blacksburg, VA
PUF RO (RING OSCILLATOR)
PUF RO (RING OSCILLATOR) EEC 492/592, CIS 493 Hands-on Experience on Computer System Security Chan Yu Cleveland State University CIRCUIT PUF - PREVIOUS WORK Ravikanth et. al proposed the first PUF in literature
Active and Passive Side-Channel Attacks on Delay Based PUF Designs
1 Active and Passive Side-Channel Attacks on Delay Based PUF Designs Georg T. Becker, Raghavan Kumar Abstract Physical Unclonable Functions (PUFs) have emerged as a lightweight alternative to traditional
SPARKS Smart Grids Week Stakeholder Workshop
SPARKS Smart Grids Week Stakeholder Workshop Smart meter (gateway) authentication and key management using hardware PUFs Physical structures are unique every physical object is unique, has a specific fingerprint
A PUF Design for Secure FPGA-Based Embedded Systems
A PUF Design for Secure FPGA-Based Embedded Systems author line author line2 author line3 Abstract The concept of having an integrated circuit (IC) generate its own unique digital signature has broad application
Reliable and efficient PUF-based key generation using pattern matching
Reliable and efficient PUF-based key generation using pattern matching The MIT Faculty has made this article openly available. Please share how this access benefits you. Your story matters. Citation As
Dopingless Transistor based Hybrid Oscillator Arbiter Physical Unclonable Function
Dopingless Transistor based Hybrid Oscillator Arbiter Physical Unclonable Function V. P. Yanambaka 1, S. P. Mohanty 2, E. Kougianos 3, P. Sundaravadivel 4 and J. Singh 5 NanoSystem Design Laboratory (NSDL,
PUF Modeling Attacks: An Introduction and Overview
PUF Modeling Attacks: An Introduction and Overview Ulrich Rührmair Technische Universität München 80333 München, Germany E-mail: ruehrmair@ilo.de Jan Sölter Freie Universität Berlin 14195 Berlin, Germany
AFRL-RI-RS-TR
AFRL-RI-RS-TR-2014-018 IC PIRACY PROTECTION BY APUF AND LOGIC OBFUSCATION RICE UNIVERSITY JANUARY 2014 FINAL TECHNICAL REPORT STINFO COPY AIR FORCE RESEARCH LABORATORY INFORMATION DIRECTORATE AIR FORCE
A Physical Unclonable Function based on Capacitor Mismatch in a Charge-Redistribution SAR-ADC
A Physical Unclonable Function based on Capacitor Mismatch in a Charge-Redistribution SAR-ADC Qianying Tang, Won Ho Choi, Luke Everson, Keshab K. Parhi and Chris H. Kim University of Minnesota Department
Ultra-lightweight and Reconfigurable Tristate Inverter Based Physical Unclonable Function Design
Ultra-lightweight and Reconfigurable Inverter Based Physical Unclonable Function Design Cui, Y., Gu, C., Wang, C., O'Neill, M., & Liu, W. (2018). Ultra-lightweight and Reconfigurable Inverter Based Physical
Physical Unclonable Functions and Applications: A Tutorial
INVITED PAPER Physical Unclonable Functions and Applications: A Tutorial This paper is a tutorial on ongoing work in physical-disorder-based security, security analysis, and implementation choices. By
Adapting Voltage Ramp-up Time for Temperature Noise Reduction on Memory-based PUFs
Adapting Voltage Ramp-up Time for Temperature Noise Reduction on Memory-based PUFs Mafalda Cortez Said Hamdioui Delft University of Technology Faculty of EE, Mathematics and CS Mekelweg 4, 2628 CD Delft,
REPORT DOCUMENTATION PAGE
REPORT DOCUMENTATION PAGE Form Approved OMB No. 74-88 The public reporting burden for this collection of information is estimated to average hour per response, including the time for reviewing instructions,
Processor-Based Strong Physical Unclonable Functions with Aging-Based Response Tuning
IEEE TRANSACTIONS ON EMERGING TOPICS IN COMPUTING, VOL. X, NO. X, DECEMBER 213 1 Processor-Based Strong Physical Unclonable Functions with Aging-Based Response Tuning Joonho Kong, Member, IEEE, and Farinaz
A PUF Design for Secure FPGA-Based Embedded Systems
A PUF Design for Secure FPGA-Based Embedded Systems Jason H. Anderson Department of Electrical and Computer Engineering University of Toronto Toronto, Ontario, Canada e-mail: janders@eecg.toronto.edu Abstract
Performance Metrics and Empirical Results of a PUF Cryptographic Key Generation ASIC
Performance Metrics and Empirical Results of a PUF Cryptographic Key Generation ASIC The MIT Faculty has made this article openly available. Please share how this access benefits you. Your story matters.
Microprocessor Based Physical Unclonable Function
Microprocessor Based Physical Unclonable Function Sudeendra kumar K, Sauvagya Sahoo, Abhishek Mahapatra, Ayas Kanta Swain, K.K.Mahapatra kumar.sudeendra@gmail.com, sauvagya.nitrkl@gmail.com, kmaha2@gmail.com
Robust and Reverse-Engineering Resilient PUF Authentication and Key-Exchange by Substring Matching
Received 10 May 2013; revised 9 October 2013; accepted 22 December 2013. Date of publication xx xxx xxxx; date of current version xx xxx xxxx. Digital Object Identifier 10.1109/TETC.2014.2300635 Robust
Novel Reconfigurable Silicon Physical Unclonable Functions
Novel Reconfigurable Silicon Physical Unclonable Functions Yingjie Lao and Keshab K. Parhi epartment of Electrical and Computer Engineering, University of Minnesota, Twin Cities {laoxx25, parhi}@umn.edu
Soft Response Generation and Thresholding Strategies for Linear and Feed-Forward MUX PUFs
Soft esponse Generation and Thresholding Strategies for Linear and Feed-Forward MUX PUFs Chen Zhou, Saroj Satapathy, Yingjie Lao, Keshab K. Parhi and Chris H. Kim Department of ECE, University of Minnesota,
Robust and Reverse-Engineering Resilient PUF Authentication and Key-Exchange by Substring Matching
.9/TETC.24.23635, IEEE Transactions on Emerging Topics in Computing Robust and Reverse-Engineering Resilient PUF Authentication and Key-Exchange by Substring Matching Masoud Rostami, Mehrdad Majzoobi,
Lightweight and Secure PUF Key Storage Using Limits of Machine Learning
Lightweight and Secure PUF Key Storage Using Limits of Machine Learning Meng-Day (Mandel) Yu 1, David M Raihi 1, Richard Sowell 1, and Srinivas Devadas 2 1 Verayo Inc., San Jose, CA, USA {myu,david,rsowell}@verayo.com
High Reliability PUF using Hot-Carrier Injection Based Response Reinforcement
High Reliability PUF using Hot-Carrier Injection Based Response Reinforcement Mudit Bhargava and Ken Mai Electrical and Computer Engineering Carnegie Mellon University CHES 2013 Key Generation using PUFs
The PUF Promise (Short Paper)
The PUF Promise (Short Paper) Heike Busch 1, Miroslava Sotáková 2, Stefan Katzenbeisser 1, and Radu Sion 2 1 Technische Universität Darmstadt 2 Stony Brook University Abstract. Physical Uncloneable Functions
ITM1010 Computer and Communication Technologies
ITM omputer and ommunication Technologies Lecture #5 Part I: Introduction to omputer Technologies K-Map, ombination and Sequential Logic ircuits ITM 計算機與通訊技術 2 Product Product-Of Of-Sum onfiguration Sum
How to Generate Repeatable Keys Using Physical Unclonable Functions
Noname manuscript No. (will be inserted by the editor) How to Generate Repeatable Keys Using Physical Unclonable Functions Correcting PUF Errors with Iteratively Broadening and Prioritized Search Nathan
Statistical Static Timing Analysis: How simple can we get?
Statistical Static Timing Analysis: How simple can we get? Chirayu Amin, Noel Menezes *, Kip Killpack *, Florentin Dartu *, Umakanta Choudhury *, Nagib Hakim *, Yehea Ismail ECE Department Northwestern
Physically Unclonable Functions: a Study on the State of the Art and Future Research Directions.
Physically Unclonable Functions: a Study on the State of the Art and Future Research Directions. Roel Maes, Ingrid Verbauwhede 1 Introduction The idea of using intrinsic random physical features to identify
PHYSICAL UNCLONABLE FUNCTION HARDWARE KEYS UTILIZING KIRCHHOFF-LAW-JOHNSON-NOISE SECURE KEY EXCHANGE AND NOISE-BASED LOGIC
Fluctuation and Noise Letters Vol. 12, No. 3 (2013) 1350018 (11 pages) c World Scientific Publishing Company DOI: 10.1142/S0219477513500181 PHYSICAL UNCLONABLE FUNCTION HARDWARE KEYS UTILIZING KIRCHHOFF-LAW-JOHNSON-NOISE
PUF Design - User Interface
PUF Design - User Interface September 27, 2011 1 Introduction Design an efficient Physical Unclonable Functions (PUF): PUFs are low-cost security primitives required to protect intellectual properties
arxiv: v1 [cs.cr] 26 Jan 2015
![arxiv: v1 [cs.cr] 26 Jan 2015](/thumbs/76/73323654.jpg "arxiv: v1 [cs.cr] 26 Jan 2015")
A new Definition and Classification of Physical Unclonable Functions arxiv:1501.06363v1 [cs.cr] 26 Jan 2015 ABSTRACT Rainer Plaga Federal Office for Information Security (BSI) Godesberger Allee 185-189
A Heuristic Method for Statistical Digital Circuit Sizing
A Heuristic Method for Statistical Digital Circuit Sizing Stephen Boyd Seung-Jean Kim Dinesh Patil Mark Horowitz Microlithography 06 2/23/06 Statistical variation in digital circuits growing in importance
Realization of MUX-Based PUF for low power applications
IOSR Journal of Electronics and Communication Engineering (IOSR-JECE) e-issn: 2278-2834,p- ISSN: 2278-8735.Volume 11, Issue 6, Ver. IV (Nov.-Dec.2016), PP 33-43 www.iosrjournals.org Realization of MUX-Based
The DRAM Latency PUF:
The DRAM Latency PUF: Quickly Evaluating Physical Unclonable Functions by Exploiting the Latency-Reliability Tradeoff in Modern Commodity DRAM Devices Jeremie S. Kim Minesh Patel Hasan Hassan Onur Mutlu
Application-Based Performance and Power Analysis on Dynamically Reconfigurable Processor
223 8522 3-4- E-mail: drp@am.ics.keio.ac.jp NEC Dynamically Reconfigurable Processor (DRP) DRP, Abstract Application-Based Performance and Power Analysis on Dynamically Reconfigurable Processor Yohei HASEGAWA,
Bits and Bit Patterns. Chapter 1: Data Storage (continued) Chapter 1: Data Storage
Chapter 1: Data Storage Computer Science: An Overview by J. Glenn Brookshear Chapter 1: Data Storage 1.1 Bits and Their Storage 1.2 Main Memory 1.3 Mass Storage 1.4 Representing Information as Bit Patterns
Intrinsic Rowhammer PUFs: Leveraging the Rowhammer Effect for Improved Security
Intrinsic Rowhammer PUFs: Leveraging the Rowhammer Effect for Improved Security André Schaller, Wenjie Xiong, Nikolaos Athanasios Anagnostopoulos, Muhammad Umair Saleem, Sebastian Gabmeyer, Stefan Katzenbeisser
RRAM-based PUF: Design and Applications in Cryptography. Ayush Shrivastava
RRAM-based PUF: Design and Applications in Cryptography by Ayush Shrivastava A Thesis Presented in Partial Fulfillment of the Requirements for the Degree Master of Science Approved July 2015 by the Graduate
CS599: Algorithm Design in Strategic Settings Fall 2012 Lecture 6: Prior-Free Single-Parameter Mechanism Design (Continued)
CS599: Algorithm Design in Strategic Settings Fall 2012 Lecture 6: Prior-Free Single-Parameter Mechanism Design (Continued) Instructor: Shaddin Dughmi Administrivia Homework 1 due today. Homework 2 out
Finite state machines (cont d)
Finite state machines (cont d)! Another type of shift register " Linear-feedback shift register (LFSR)! Used to generate pseudo-random numbers! Some FSM examples Autumn 2014 CSE390C - VIII - Finite State
FSM Optimization. Outline. FSM State Minimization. Some Definitions. Methods 10/14/2015
/4/25 C2: Digital Design http://jatinga.iitg.ernet.in/~asahu/cs22 FSM Optimization Outline FSM : State minimization Row Matching Method, Implication chart method, FSM Partitioning FSM Encoding: Random,
Differential Return Loss for Clause 137 and Matched COM Package Parameters For Comments #92 and #93 Richard Mellitz, Samtec
Differential Return Loss for Clause 137 and Matched COM Package Parameters For Comments #92 and #93 Richard Mellitz, Samtec March 2017 IEEE802.3 Plenary, Vancouver, BC, Canada 1 IEEE P802.3 50 Gb/s, 100
Protocol Attacks on Advanced PUF Protocols and Countermeasures
Protocol Attacks on Advanced PUF Protocols and Countermeasures Marten van Dijk University of Connecticut Storrs, CT 06269, USA E-mail: vandijk@engr.uconn.edu Ulrich Rührmair Technische Universität München
Prudential sourcebook for Banks, Building Societies and Investment Firms. Chapter 13
Prudential sourcebook for Banks, Building Societies and Investment Firms Chapter The calculation of values for financial derivatives, securities financing transactions and long settlement transactions
14.02 Quiz 1. Time Allowed: 90 minutes. Spring 2014
14.02 Quiz 1 Time Allowed: 90 minutes Spring 2014 NAME: MIT ID: FRIDAY RECITATION: FRIDAY RECITATION TA: This quiz has a total of 3 parts/questions. The first part has 10 multiple choice questions where
RELATIVE CURRENCY STRENGTH -ADDON-
RELATIVE CURRENCY STRENGTH -ADDON- TABLE OF CONTENTS INSTRUCTIONS FOR PACKAGE INSTALLATION 3 USING RELATIVE CURRENCY STRENGTH (RCS) 4 PARAMETERS 4 SIGNALS 5 2 INSTRUCTIONS FOR PACKAGE INSTALLATION 1. As
Lecture 20: Sequential Circuits. Sequencing
Lecture 20: Sequential Circuits Sequencing Elements Simple /FF Timing efinitions Source: Ch 7 (W&H) Sequencing Use flip-flops to delay fast tokens so they move through exactly one stage each cycle. Inevitably
International Journal of Computer Science Trends and Technology (IJCST) Volume 5 Issue 2, Mar Apr 2017
RESEARCH ARTICLE Stock Selection using Principal Component Analysis with Differential Evolution Dr. Balamurugan.A [1], Arul Selvi. S [2], Syedhussian.A [3], Nithin.A [4] [3] & [4] Professor [1], Assistant
EE115C Spring 2013 Digital Electronic Circuits. Lecture 19: Timing Analysis
EE115C Spring 2013 Digital Electronic Circuits Lecture 19: Timing Analysis Outline Timing parameters Clock nonidealities (skew and jitter) Impact of Clk skew on timing Impact of Clk jitter on timing Flip-flop-
Reconfigurable Acceleration for Monte Carlo based Financial Simulation
Reconfigurable Acceleration for Monte Carlo based Financial Simulation G.L. Zhang, P.H.W. Leong, C.H. Ho, K.H. Tsoi, C.C.C. Cheung*, D. Lee**, Ray C.C. Cheung*** and W. Luk*** The Chinese University of
Chapter Twenty 11/26/2017. Chapter 20 Money Growth, Money Demand, and Modern Monetary Policy. In This Chapter. 1. The quantity theory of money.
Chapter Twenty Chapter 20 Money Growth, Money Demand, and Modern Monetary Policy In This Chapter 1. The quantity theory of money. 2. The velocity of, and demand for, money. 3. Money targeting. Money Growth
A Formal Study of Distributed Resource Allocation Strategies in Multi-Agent Systems
A Formal Study of Distributed Resource Allocation Strategies in Multi-Agent Systems Jiaying Shen, Micah Adler, Victor Lesser Department of Computer Science University of Massachusetts Amherst, MA 13 Abstract
Accelerating Financial Computation
Accelerating Financial Computation Wayne Luk Department of Computing Imperial College London HPC Finance Conference and Training Event Computational Methods and Technologies for Finance 13 May 2013 1 Accelerated
Genetic Algorithm-based Electromagnetic Fault Injection
Genetic Algorithm-based Electromagnetic Fault Injection Antun Maldini Niels Samwel Stjepan Picek Lejla Batina Institute for Computing and Information Sciences Digital Security FDTC 2018 2018-09-13 Antun
Delay Budgeting in Sequential Circuit with Application on FPGA Placement
13.2 Delay Budgeting in Sequential Circuit with Application on FPGA Placement Chao-Yang Yeh and Malgorzata Marek-Sadowska Department of Electrical and Computer Engineering, University of California, Santa
Lecture 8: Skew Tolerant Design (including Dynamic Circuit Issues)
Lecture 8: Skew Tolerant Design (including Dynamic Circuit Issues) Computer Systems Laboratory Stanford University horowitz@stanford.edu Copyright 2007 by Mark Horowitz w/ material from David Harris 1
Sequential Gates. Gate Level Design. Young Won Lim 3/15/16
equential Gates Gate Level esign Copyright (c) 2011-2016 Young W. Lim. Permission is granted to copy, distribute and/or modify this document under the terms of the GNU Free ocumentation License, Version
Barrier Option. 2 of 33 3/13/2014
FPGA-based Reconfigurable Computing for Pricing Multi-Asset Barrier Options RAHUL SRIDHARAN, GEORGE COOKE, KENNETH HILL, HERMAN LAM, ALAN GEORGE, SAAHPC '12, PROCEEDINGS OF THE 2012 SYMPOSIUM ON APPLICATION
Capacity Performance Transition Incremental Auctions Rules, Schedule and Planning Parameters
Capacity Performance Transition Incremental Auctions Rules, Schedule and Planning Parameters Overview Capacity Performance Transition Incremental Auctions will be conducted for the 2016/2017 and 2017/2018
Familiarize yourself with the concept of Physical Unclonable Functions (PUFs). Pay special attention to memory (SRAM) based PUFs.
Familiarize yourself with the concept of Physical Unclonable Functions (PUFs). Pay special attention to memory (SRAM) based PUFs. Analyze existing measurements of initial SRAM contents in Atmel ATmega1284
Notes on Estimating the Closed Form of the Hybrid New Phillips Curve
Notes on Estimating the Closed Form of the Hybrid New Phillips Curve Jordi Galí, Mark Gertler and J. David López-Salido Preliminary draft, June 2001 Abstract Galí and Gertler (1999) developed a hybrid
We consider three zero-coupon bonds (strips) with the following features: Bond Maturity (years) Price Bond Bond Bond
15 3 CHAPTER 3 Problems Exercise 3.1 We consider three zero-coupon bonds (strips) with the following features: Each strip delivers $100 at maturity. Bond Maturity (years) Price Bond 1 1 96.43 Bond 2 2
Noncooperative Market Games in Normal Form
Chapter 6 Noncooperative Market Games in Normal Form 1 Market game: one seller and one buyer 2 players, a buyer and a seller Buyer receives red card Ace=11, King = Queen = Jack = 10, 9,, 2 Number represents
Direct Anonymous Attestation & TPM2.0 Getting Provably Secure Crypto into the Real-World. Anja Lehmann IBM Research Zurich
Direct Anonymous Attestation & 2.0 Getting Provably Secure Crypto into the Real-World Anja Lehmann IBM Research Zurich Direct Anonymous Attestation & Trusted Platform Module () Secure crypto processor:
High throughput implementation of the new Secure Hash Algorithm through partial unrolling
High throughput implementation of the new Secure Hash Algorithm through partial unrolling Konstantinos Aisopos Athanasios P. Kakarountas Haralambos Michail Costas E. Goutis Dpt. of Electrical and Computer
CS 237: Probability in Computing
CS 237: Probability in Computing Wayne Snyder Computer Science Department Boston University Lecture 12: Continuous Distributions Uniform Distribution Normal Distribution (motivation) Discrete vs Continuous
Chapter 7. Registers & Register Transfers. J.J. Shann. J. J. Shann
Chapter 7 Registers & Register Transfers J. J. Shann J.J. Shann Chapter Overview 7-1 Registers and Load Enable 7-2 Register Transfers 7-3 Register Transfer Operations 7-4 A Note for VHDL and Verilog Users
READING AND UNDERSTANDING FINANCIAL STATEMENTS
READING AND UNDERSTANDING FINANCIAL STATEMENTS WHY DO YOU WANT TO UNDERSTAND FINANCIALS? Gives you clarity about your business s health Allows you to talk with confidence about your business (banks, investors,
Square D Modbus Solution: Altivar 58 VFD
Point Map November 1, 2004 Systems Integration Square D Modbus Solution: Altivar 58 VFD Table 1. Altivar 58 VFD Point Map, Application 4509. 1 LAO Slave Address 1to247 2 LAI Application Number 4509 3 LDI
Determination of Insurance Policy Using a hybrid model of AHP, Fuzzy Logic, and Delphi Technique: A Case Study
Determination of Insurance Policy Using a hybrid model of AHP, Fuzzy Logic, and Delphi Technique: A Case Study CHIN-SHENG HUANG, YU-JU LIN 2, CHE-CHERN LIN 3 : Department and Graduate Institute of Finance,
Great Basin College Courses (BUS) - Economics
Course Assessment Report - 4 Column Great Basin College Courses (BUS) - Economics Course Outcomes Means of Assessment & Criteria / Tasks Results Action & Follow-Up Prin of Microeconomics - Define and Distinguish
Creating Shared Value through ESG Portfolios. A division of RTI International
Creating Shared Value through ESG Portfolios Summary The concept of Creating Shared Value (CSV), first introduced as an idea to align competitive advantage and financial returns with corporate social responsibility
Lecture 7. Analysis of algorithms: Amortized Analysis. January Lecture 7
Analysis of algorithms: Amortized Analysis January 2014 What is amortized analysis? Amortized analysis: set of techniques (Aggregate method, Accounting method, Potential method) for proving upper (worst-case)
Analytics in 10 Micro-Seconds Using FPGAs. David B. Thomas Imperial College London
Analytics in 10 Micro-Seconds Using FPGAs David B. Thomas dt10@imperial.ac.uk Imperial College London Overview 1. The case for low-latency computation 2. Quasi-Random Monte-Carlo in 10us 3. Binomial Trees
Schwab RT SQL Recordkeeping Operations Library Multi-Process Configuration Guide for Users of ACA, Online Enrollment (Legacy), and Eligibility
Schwab RT SQL Recordkeeping Operations Library Multi-Process Configuration Guide for Users of ACA, Online Enrollment (Legacy), and Eligibility Notes: For users of Schwab RT Web 4.0, refer to Online Enrollment
Unit 2: Modeling in the Frequency Domain Part 2: The Laplace Transform
The Laplace Transform Unit 2: Modeling in the Frequency Domain Part 2: The Laplace Transform Engineering 5821: Control Systems I Faculty of Engineering & Applied Science Memorial University of Newfoundland
Chapter 1: Data Storage
Chapter 1: Data Storage Computer Science: An Overview Tenth Edition by J. Glenn Brookshear Copyright 2008 Pearson Education, Inc. Publishing as Pearson Addison-Wesley Chapter 1: Data Storage 1.1 Bits and
Evolutionary voting games. Master s thesis in Complex Adaptive Systems CARL FREDRIKSSON
Evolutionary voting games Master s thesis in Complex Adaptive Systems CARL FREDRIKSSON Department of Space, Earth and Environment CHALMERS UNIVERSITY OF TECHNOLOGY Gothenburg, Sweden 2018 Master s thesis
Unit M2.2 (All About) Stress
Unit M. (All About) Stress Readings: CDL 4., 4.3, 4.4 16.001/00 -- Unified Engineering Department of Aeronautics and Astronautics Massachusetts Institute of Technology LEARNING OBJECTIVES FOR UNIT M. Through
(12) (10) Patent No.: US 8,848,905 B1. Hamlet et al. (45) Date of Patent: Sep. 30, 2014
United States Patent USOO8848905B1 (12) (10) Patent No.: Hamlet et al. (45) Date of Patent: Sep. 30, 2014 (54) DETERRENCE OF DEVICE 6,009,549 A * 12/1999 Bliss et al.... T14f769 7,370,190 B2 5/2008 Calhoon
Annex Guidelines on Standardised Approach for Counterparty Credit Risk (SA-CCR)
Annex Guidelines on Standardised Approach for Counterparty Credit Risk (SA-CCR) Para 5.15.3.5 of Basel III Capital Framework on Default Risk Capital Charge will be replaced by the following framework.
Global Value Chains, Foreign Direct Investment, and Taxation
Global Value Chains, Global Value Chains, Bev Dahlby * University of Alberta 1.0 Introduction This research volume is concerned with the causes and consequences of global value chains the fragmentation
Center for Networked Computing
Motivation Model and problem formulation Theoretical analysis The idea of the proposed algorithm Performance evaluations Data downloading during the driving Self-driving vehicles Traffic and safety information
Application of Deep Learning to Algorithmic Trading
Application of Deep Learning to Algorithmic Trading Guanting Chen [guanting] 1, Yatong Chen [yatong] 2, and Takahiro Fushimi [tfushimi] 3 1 Institute of Computational and Mathematical Engineering, Stanford
Problems and Solutions
1 CHAPTER 1 Problems 1.1 Problems on Bonds Exercise 1.1 On 12/04/01, consider a fixed-coupon bond whose features are the following: face value: $1,000 coupon rate: 8% coupon frequency: semiannual maturity:
13 Combinational Logic Devices
Prof. r. J. Reichardt Prof. r.. Schwarz F Elektrotechnik/Informatik ombinational ogic evices Purpose of combinational logic design: uilding larger, more sophisticated logic circuits by using adaptable