Operational Amplifier Stability. Collin Wells Texas Instruments HPA Linear Applications 2/22/2012

Transcription

1 Operational Amplifier Stability Collin Wells Texas Instruments HPA Linear Applications 2/22/212 1

2 The Culprits Capacitive Loads! Reference Buffers! Cable/Shield Drive! MOSFET Gate Drive! Rg 1k Rf 2k Q1 VReg VIN 5 Cin 1u U1 REF525 Vin ut Temp GND Trim C1 1u OPA C3 1u C2 1u Vin ADC_VREF C4 1n VREF 2.5 OPA OPA Shielded Cable C_Cable 1n ut RL 25 VREF Vin 1 OPA VRef 2.5 R1 2k R2 2k RL 2 Id Transimpedance Amplifiers! Photodiode Model Rd 4.99G Cd 1p High Feedback Network Impedance! Rf 1M OPA VG2 HighSource Impedance or LowPower Circuits! R4 499k Cin 25p R3 499k IOP2 ut Rg 4.99M Vin TVS Attenuators! D1 D2 V Cd 2p Rf 49k OPA ut 2

3 Just Plain Trouble! Inverting Input Filter?? Oscillator Rg 1k Rf 1k 1.m m Vin Cin 1u OPA ut Vfb 37.8m m 2.23m 2.5m Time (s) Output Filter?? Oscillator 1.m V1 5 R1 1k R2 49k OPA C1 1u ut C5 1n Vfb m 37.8m m 2.23m 2.5m Time (s) 3

4 Recognize Amplifier Stability Issues on the Bench Required Tools: Oscilloscope Step Generator Other Useful Tools: Gain / Phase Analyzer Network / Spectrum Analyzer 4

5 Output ltage (V) ltage (V) Recognize Amplifier Stability Issues Oscilloscope Transient Domain Analysis: Oscillations or Ringing Overshoots Unstable DC ltages High Distortion 18.53m. 1.75m 2.25m 2.75m Time (s) m m 5.88m 1.m Time (s). 1.75m 2.25m 2.75m Time (s) 5

6 Phase [deg] Gain (db) Recognize Amplifier Stability Issues Gain / Phase Analyzer Frequency Domain: Peaking, Unexpected Gains, Rapid Phase Shifts k 1.k 1.k 1.M 1.M 1.M 6

7 Quick OpAmp Theory and Bode Plot Review 7

8 Poles and Bode Plots G f P A = V OUT /V IN 1 8 Actual Function.77G = 3dB StraightLine Approximation 2dB/Decade 6dB/Octave V IN X1, R C V OUT A (db) 6 4 Single Pole Circuit Equivalent k 1k 1k 1M 1M Pole Location = f P Magnitude = 2dB/Decade Slope Slope begins at f P and continues down as frequency increases (degrees) 45 o 1 1 1k 1k 1k 1M 1M 45 o /Decade Frequency (Hz) Actual Function = 3dB f P Phase = 45 /Decade Slope through f P Decade Above f P Phase = f P Decade Below f P Phase = o 8

9 1 8 Zeros and Bode Plots X1, A = V OUT /V IN C V OUT A (db) 6 2dB/Decade 6dB/Octave R G = 3dB (1/.77)G = 3dB G Actual Function StraightLine Approximation Single Zero Circuit Equivalent f Z 1k 1k 1k 1M 9 o 1M Zero Location = f Z Magnitude = 2dB/Decade Slope o /Decade Slope begins at f Z and continues up as frequency increases (degrees) o 45 f Z 1 1 1k 1k 1k 1M 1M Frequency (Hz) Actual Function = 3dB f Z Phase = 45 /Decade Slope through f Z 45 Decade Above f Z Phase = Decade Below f Z Phase = 5.7 9

10 Capacitor Intuitive Model DC X C DC < X C < Hif Hif X C OPEN SHORT frequency controlled resistor X C = 1/(2 fc) 1

11 Inductor Intuitive Model DC X L DC < X L < Hif Hif X L SHORT OPEN frequency controlled resistor X L = 2 fl 11

12 OpAmp Intuitive Model IN Rin INx1 Vdiff K(f) Ro ut 12

13 OpAmp Loop Gain Model network RF network =V FB /V OUT RI V FB V OUT V OUT RF V IN V FB RI V OUT /V IN = Acl = Aol/(1Aolβ) If Aol >> 1 then Acl 1/β V IN Aol V OUT Aol: Open Loop Gain β: Feedback Factor Acl: Closed Loop Gain 13

14 Amplifier Stability Criteria V OUT /V IN = Aol / (1 Aolβ) If: Aolβ = 1 Then: V OUT /V IN = Aol / If V OUT /V IN = Unbounded Gain Any small changes in V IN will result in large changes in V OUT which will feed back to V IN and result in even larger changes in V OUT OSCILLATIONS INSTABILITY!! Aolβ: Loop Gain Aolβ = 1 Phase shift of 18, Magnitude of 1 (db) fcl: frequency where Aolβ = 1 (db) Stability Criteria: At fcl, where Aolβ = 1 (db), Phase Shift < 18 Desired Phase Margin (distance from 18 Phase Shift) > 45 14

15 What causes amplifier stability issues??? 15

16 Fundamental Cause of Amplifier Stability Issues Too much delay in the feedback network R2 1k Vfb DELAY R1 1k DELAY BUF 16

17 Cause of Amplifier Stability Issues Example circuit with too much delay in the feedback network Vfb DELAY DELAY R2 1k R1 1k R3 1 C2 2p C1 1u BUF 1.m m Vfb 37.8m m 2.23m 2.5m Time (s) 17

18 Cause of Amplifier Stability Issues Real circuit translation of too much delay in the feedback network R2 1k Vfb R1 1k R3 1 C2 2p C1 1u BUF R2 1k Vfb R1 1k Cstray 16p Cin 4p BUF Ro 1 Cload 1u 18

19 Cause of Amplifier Stability Issues Same results as the example circuit Vfb R2 1k R1 1k Cstray 16p Cin 4p BUF Ro 1 Cload 1u 1.m m Vfb 37.8m m 2.23m 2.5m Time (s) 19

20 How do we determine if our system has too much delay?? 2

21 Phase Margin Gain (db) Phase Margin is a measure of the delay in the loop AOL 1/Beta (UnityGain) fcl n V VF1 OpenLoop U2 OPA627E V Phase (degrees) AOL Phase Phase Margin k 1.k 1k 1.k 1k 1.k 1M 1.M 1M 1.M 1M 1.M 21

22 Damping Ratio vs. Phase Margin From: Dorf, Richard C. Modern Control Systems. AddisonWesley Publishing Company. Reading, Massachusetts. Third Edition,

23 SmallSignal Overshoot vs. Damping Ratio Phase Margin Overshoot 9 8 2% 7 5% 6 1% 5 16% 4 25% 3 37% 2 53% 1 73% From: Dorf, Richard C. Modern Control Systems. AddisonWesley Publishing Company. Reading, Massachusetts. Third Edition,

24 AC Peaking vs. Damping Ratio Phase Margin AC 9 7dB 8 5dB 7 4dB 6 1dB 5 1dB 4 3dB 3 6dB 2 9dB 1 14dB From: Dorf, Richard C. Modern Control Systems. Addison Wesley Publishing Company. Reading, Massachusetts. Third Edition,

25 Rate of Closure Rate of Closure: Rate at which 1/Beta and AOL intersect ROC = Slope(1/Beta) Slope(AOL) ROC = db/decade (2dB/decade) = 2dB/decade 12 1 AOL Gain (db) AOL*B 1/Beta Rate of Closure = 2dB/decade fcl k 1.k 1.k 1.M 1.M 1.M 1 1k 1k 1k 1M 1M 1M 25

26 Rate of Closure and Phase Margin Relationship between the AOL and 1/Beta rate of closure and Loop Gain (AOL*B) phase margin Gain (db) Phase (degrees) AOL AOL*B 1/B AOL*B Phase Rate of Closure = 2dB/decade Phase Margin 45 degrees! k 1k 1k 1M 1M 1M 26

27 Rate of Closure and Phase Margin 12 So a pole in AOL or a zero in 1/Beta inside the loop will decrease AOL*B Phase!! 1 8 AOL AOL pole Gain (db) /Beta 4dB/decade 4dB/decade 2 4 1/B zero k 1k 1k 1M 1M 1M k 1.k 1.k 1.M 1.M 1.M 27

28 Rate of Closure and Phase Margin AOL Pole Gain (db) Phase (degrees) Pole in AOL Rate of Closure = 4dB/decade! Phase Margin degrees! k 1.k 1.k 1.M 1.M 1.M 1 1k 1k 1k 1M 1M 1M 1/Beta Zero Gain (db) Phase (degrees) Zero in 1/B Rate of Closure = 4dB/decade! Phase Margin degrees! k 1.k 1.k 1.M 1.M 1.M 1 1k 1k 1k 1M 1M 1M 28

29 Testing for Rate of Closure in SPICE Break the feedback loop and inject a small AC signal R1 1k R2 1k V VF1 V U2 OPA627E Vfb R3 1k R4 1k Short out the input source L1 1T Vin V Break the loop with L1 at the inverting input C1 1T VG2 V U1 OPA627E Inject an AC stimulus through C1 29

30 Breaking the Loop Rg 1k Vfb DC Rf 1k Vin AC V L1 C1 Vin V U1 OPA627E L1 C1 VG2 V U1 OPA627E Rf 1k Vfb V Rg 1k 3

31 Plotting AOL, 1/Beta, and Loop Gain Gain (db) Rg 1k Vfb L1 1T C1 1T Vin Rf 1k V V U1 OPA627E AOL*B 1/B AOL = /Vin 1/Beta = /Vfb AOL*B = Vfb/Vin AOL Phase (degrees) AOL*B Phase Phase Margin = 8degrees k 1k 14.14k 1k 1M 1M 1M 2.M 31

32 Noise Gain Understanding Noise Gain vs. Signal Gain Signal Gain, G = 1 Signal Gain, G = 2 R1 1k R2 1k R1 1k R2 1k V V V U1 OPA627E V U1 OPA627E NG = 1 ΙSGΙ = 2 NG = SG = 2 Both circuits have a NOISE GAIN (NG) of 2. 32

33 Noise Gain Noise Gain vs. Signal Gain Gain of.1v/v, Is it Stable? Signal Gain, G =.1 Noise Gain, NG = 1.1 R1 1k R2 1k R1 1k R2 1k V V V U1 OPA627E V U1 OPA627E If it s unitygain stable then it s stable as an inverting attenuator!!! 33

34 Capacitive Loads 34

35 Capacitive Loads Unity Gain Buffer Circuits R3 4.99k Circuits with Gain R2 1k V V Vin U1 OPA627E V CLoad 1uF Vin V U1 OPA627E CLoad 1u 8m 4m (V) 2m (V) 2m 4m 2m 1m Vin (V) 1m Vin (V) 15u 3u Time (seconds) 15u 3u 35 Time (seconds)

36 Capacitive Loads Unity Gain Buffers Results Determine the issue: Pole in AOL!! ROC = 4dB/decade!! C4 1T L1 1T Vin Phase Margin!! Vin V V U1 OPA627E Gain (db) CLoad 1u AOL AOL*B 1/B NG = 1V/V = db Pole in AOL Rate of Closure = 4dB/decade! Phase (degrees) AOL*B Phase Phase Margin =.2degrees! k 1.k 1k 1.k 1k 1.k 1M 1.M 1M 1.M 1M 1.M 36

37 C4 1T Capacitive Loads Unity Gain Buffers Theory L1 1T Vin V Ro 54 Vin U1 OPA627E V CLoad 1u AOL CLoad 1u Loaded AOL L1 C1 Vin AOL 1M Ro 54 CLoad 1u Loaded AOL 37

38 Capacitive Loads Unity Gain Buffers Theory Ro 54 2 Vin Loaded AOL CLoad 1u Gain (db) 4 6 Loaded AOL Pole Transfer function: 1 W(s)= 1R o C load s 1 f(pole)= 2 pi R o C Load s Phase (degrees) k 1.k 1.k 1.M 1.M 1.M 1 1k 1k 1k 1M 1M 1M 38

39 Gain (db) ltage (V) ltage (V) Phase (degrees) Capacitive Loads Unity Gain Buffers Theory AOL X Gain (db) Phase (degrees) AOL Load k 1.k 1k 1.k 1k 1.k 1M 1.M 1M 1.M 1M 1.M Loaded AOL = Gain (db) k 1k 1.k 1k 1.k 1k 1.M 1M 1.M 1M 1.M 1M Phase (degrees) k 1.k 1.k 1.k 1.M 1.M 1.M Frequency 1k (Hz) 1k 1M 1M 1M 39

40 Stabilize Capacitive Loads Unity Gain Buffers 4

41 Stability Options UnityGain circuits can only be stabilized by modifying the AOL load Gain (db) k 1.k 1.k 1.M 1.M 1.M 1 1k 1k 1k 1M 1M 1M 41

42 Method 1: Riso V V U1 OPA627E Riso 6 VLoad CLoad 1u 42

43 Method 1: Riso Results Theory: Adds a zero to the Loaded AOL response to cancel the pole 12 1 L1 1T C1 1T Vin V V U1 OPA627E Riso 5 Gain (db) CLoad 1u AOL AOL*B 1/B Pole in AOL Ro 54 Zero in AOL Loaded AOL AOL Riso 5 Rate of Closure = 2dB/decade Phase (degrees) AOL*B Phase CLoad 1u Phase Margin = 87.5degrees! C1 1. Ro k 1.k 1.k 1.M 1.M 1.M 1k 1k 1k 1M 1M 1M AOL 1M Loaded AOL Riso 5 43 CLoad 1u

44 Method 1: Riso Results When to use: Works well when DC accuracy is not important, or when loads are very light 2.37m (V) V V U1 OPA627E Riso 6 VLoad CLoad 1u. 2.m Vload (V). 2.m Vin (V) u 25.u Time (s) 44

45 Method 1: Riso Theory L1 1T C1 1T Vin V V U1 OPA627E Riso 5 CLoad 1u AOL Ro 54 Loaded AOL Riso 5 CLoad 1u C1 AOL 1M Ro 54 Loaded AOL Riso 5 CLoad 1u 45

46 Method 1: Riso Theory Ro 54Ohm Loaded AOL Vin Riso 5Ohm CLoad 1uF Gain (db) 2 Transfer function: 1C Load R iso s Loaded AOL(s)= 1(R o R iso ) C Load s Pole Equation: 1 f(pole)= 2 pi (R o R iso ) C Load s Zero Equation: 1 f(zero)= 2 pi R iso C Load s Phase (degrees) k 1.k 1k 1.k 1k 1.k 1M 1.M 1M 1.M 1M 1.M 46

47 Gain (db) Phase [deg] Gain (db) Phase (degrees) Method 1: Riso Theory X Gain (db) Phase (degrees) k 1.k 1k 1.k 1k 1.k 1M 1.M 1M 1.M 1M 1.M = Gain (db) Phase (degrees) k 1.k 1k 1.k 1k 1.k 1M 1.M 1M 1.M 1M 1.M k 1.k 1.k 1.M 1.M 1.M 1 1k Frequency 1k (Hz) 1k 1M 1M 1M 47

48 Method 1: Riso Design Ensure Good Phase Margin: 1.) Find: fcl and f(aol = 2dB) Transfer function: 2.) Set Riso to create AOL zero: Good: f(zero) = Fcl 1C for Load PM R iso 45 sdegrees. Loaded Better: AOL(s)= f(zero) = 1(R F(AOL = 2dB) will yield slightly less than 9 degrees phase margin o R iso ) C Load s Pole Equation: fcl = kHz 1 f(aol f(pole)= = 2dB) 2 pi (R = 7.41kHz o R iso ) C Load s Zero Equation: 1 f(zero)= 2 pi R iso C Load s Gain (db) f(aol = 2dB) fcl k 1.k 1.k 1.M 1.M 1.M 1 1k 1k 1k 1M 1M 1M 48

49 Method 1: Riso Design Ensure Good Phase Margin: Test f(aol = 2dB) = 7.41kHz Riso = 2.26Ohms fcl = kHz Riso =.715Ohms Zero Equation: 1 f(zero)= 2 pi R iso C Load s L1 1T C1 1T Vin V U1 OPA627E V 2.26R 1uF L1 1T C1 1T Vin V U1 OPA627E V.715R 1uF Gain (db) F(zero) = 7.41kHz Riso 714m CLoad 1u Gain (db) Riso 714m CLoad 1u F(zero) = kHz Phase (degrees) PM = 84 Phase (degrees) PM = k 1.k 1k 1.k 1k 1.k 1M 1.M 1M 1.M 1M 1.M k 1.k 1.k 1.M 1.M 1.M 1k 1k 1k 1M 1M 1M 49

50 Method 1: Riso Design Prevent Phase Dip: Place the zero less than 1 decade from the pole, no more than 1.5 decades away Good: 1.5 Decades: F(zero) 35*F(pole) Riso Ro/34 7 Phase Shift Better: 1 Decade: F(zero) 1*F(pole) Riso Ro/9 55 Phase Shift Gain (db) F(pole) = 2.65kHz Riso = Ro/9 F(zero) = 26.5kHz Gain (db) F(pole) = 2.86kHz Riso = Ro/34 F(zero) = 1.2kHz Phase (degrees) PM_min = 35 Phase (degrees) PM_min = k 1k 1k 1M 1M 1M k 1.k 1.k 1.M 1.M 1.M 1k 1k 1k 1M 1M 1M 5

51 Method 1: Riso Design Prevent Phase Dip: Ratio of Riso to Ro If Riso 2*Ro F(zero) = 1.5*F(pole) ~1 Phase Shift **Almost completely cancels the pole. Gain (db) L1 1T C1 1T Vin V U1 OPA627E V 18R 1uF Phase (degrees) Riso = Ro*2 Riso = Ro*2 PM_min = 8 Gain (db) Phase (degrees) Phase Shift vs. Riso/Ro k 1.k 1k 1.k 1k 1.k 1M 1.M 1M 1.M 1M 1.M 51

52 Method 1: Riso Design Summary Summary: 1.) Ensure stability by placing Fzero F(AOL=2dB) 2.) If Fzero is > 1.5 decades from F(pole) then increase Riso up to at least Ro/34 3.) If loads are very light consider increasing Riso > Ro for stability across all loads L1 1T C1 1T Final Circuit Vin V V U1 OPA627E 6R 1uF Gain (db) Phase (degrees) PM_min = 35 PM = k 1.k 1k 1.k 1k 1.k 1M 1.M 1M 1.M 1M 1.M 52

53 Method 1: Riso Disadvantage Disadvantage: ltage drop across Riso may not be acceptable 2.19m V V U1 OPA627E 6R 25R Vload 1uF ltage (V) VLoad Riso ltage Drop 125u 25u Time (seconds) 53

54 Method 2: Riso Dual Feedback Rf 49k Cf 1n V V U1 OPA627E Riso 6 VLoad CLoad 1u 54

55 Method 2: Riso Dual Feedback Theory: Features a lowfrequency feedback to cancel the Riso drop and a highfrequency feedback to create the AOL pole and zero. 12 Vfb Rf 49k 1 L1 1T C1 1T Vin Cf 1n V V Riso 6 U1 OPA627E Gain (db) CLoad 1u AOL AOL*B 1/B Pole in AOL Zero in AOL Rate of Closure = 2dB/decade Phase (degrees) AOL*B Phase Phase Margin = 87.5degrees! k 1k 1k 1M 1M 1M 55

56 Method 2: Riso Dual Feedback When to Use: Only practical solution for very large capacitive loads 1uF When DC accuracy must be preserved across different current loads 2.3m R2 49k (V) C1 1n V 2m V Riso 5 U1 OPA627E Vload CLoad 1u VLoad(V) Vin(V) 2m 15u 3u Time (seconds) 56

57 Method 2: Riso Dual Feedback Design Ensure Good Phase Margin: 1.) Find: fcl and f(aol = 2dB) 2.) Set Riso to create AOL zero: Good: f(zero) = Fcl for PM 45 degrees. Transfer Better: function: f(zero) = F(AOL = 2dB) will yield slightly less than 9 degrees phase margin 3.) Set Rf so Rf >>Riso1C Load R iso s Loaded Rf AOL(s)= (Riso * 1) 1(R 4.) Set Cf (2*Riso*Cload)/Rf o R ) C Load s Pole Equation: 1 fcl f(pole)= = kHz 2 pi (R f(aol = 2dB) = 7.41kHz o R iso ) C Load s Zero Equation: 1 f(zero)= 2 pi R iso C Load s Gain (db) f(aol = 2dB) fcl k 1.k 1.k 1.M 1.M 1.M 1 1k 1k 1k 1M 1M 1M 57

58 Method 2: Riso Dual Feedback Summary Ensure Good Phase Margin (Same as Riso Method): 1.) Set Riso so f(zero) = F(AOL = 2dB) 2.) Set Rf: Rf (Riso * 1) 3.) Set Cf: Cf (2*Riso*Cload)/Rf R2 49k 12 1 C1 1n V V Riso 5 U1 OPA627E Vload CLoad 1u Gain (db) Phase (degrees) Phase Margin = 87.5degrees! k 1k 1k 1M 1M 1M 58

59 Capacitive Loads Circuits with Gain 59

60 Capacitive Loads Circuits with Gain Rg 4.99k Rf 1k V 4m V U1 OPA627E CLoad 1n 3m ltage (V) 2m 1m 15u 3u Time (seconds). 15.u 3.u 6

61 Capacitive Loads Circuits With Gain Results Same Issues as Unity Gain Circuit Pole in AOL!! ROC = 4dB/decade!! Rf 4.99k Phase Margin = 1!! Vfb L1 1T C1 1T Vin Rg 1k V V U1 OPA627E Gain (db) CLoad 1n AOL AOL*B 1/B Pole in AOL ROC = 4dB/decade Phase (degrees) AOL*B Phase PM = k 1.k 1k 1.k 1k 1.k 1M 1.M 1M 1.M 1M 1.M 61

62 Stabilize Capacitive Loads Circuits with Gain 62

63 Stability Options Circuits with Gain Circuits with gain can be stabilized by modifying the AOL load and by modifying 1/Beta 12 1 AOL Gain (db) /Beta k 1k 1k 1M 1M 1M k 1.k 1.k 1.M 1.M 1.M 63

64 Method 1 Method 2 Rg 4.99k Methods 1 and 2 work on circuits with gain as well! Method 1: Riso Rf 1k (V) 25m 25m V VLoad(V) V Riso 1 U1 OPA627E VLoad CLoad 1n Method 2: RisoDual Feedback Rg 4.99k Rf 1k Vin(V) (V) 1m 25m 15u 3u Time (seconds). 15.u 3. Cf 1p 25m V Riso 1 U1 OPA627E V VLoad CLoad 1n VLoad(V) Vin(V) 1m 15u 3u Time (seconds) u 3.

65 Method 3: Cf C1 27p Rg 4.99k Rf 1k V V U1 OPA627E CLoad 1n 65

66 Method 3: Cf Results Theory: 1/Beta compensation. Cf feedback capacitor causes 1/Beta to decrease at 2dB/decade and if placed correctly will cause the ROC to be 2dB/decade. Rg 4.99k Vfb L1 1T C1 1T VG2 Cf 27p Rf 1k Vin V V U1 OPA627E Gain (db) CLoad 1n AOL AOL*B 1/B AOL Pole 1/B Pole ROC = 2dB/decade 1/B Zero Phase (degrees) AOL*B Phase PM = k 1k 1k 1M 1M 1M 66

67 ltage (V) Method 3: Cf Results When to use: Especially effective when NG is high, 3dB. Systems where a bandwidth limitation is not an issue Limits closedloop bandwidth at 1/(2*pi*Rf*Cf) 25.m C1 27p 2.m Rg 4.99k Rf 1k V 15.m V U1 OPA627E CLoad 1n 1.m 5.m.. 15.u 3.u Time (s) 67

68 Method 3: Cf Design Ensure Good Phase Margin: For 2dB/decade ROC, 1/Beta must intersect AOL while its slope is 2dB/decade. Therefore: f(1/b pole) < f(cl_unmodified) f(1/b zero) > f(aol = db) 12 f(cl_unmodified) = kHz f(aol = db) = 74.6kHz 1 8 1/B Pole Equation: 1 f(1/b pole)= 2 pi R f C f Gain (db) f(cl_unmodified) 1/B Zero Equation: 1 f(1/b zero)= 2 pi (R g R f ) C f 2 4 f(aol = db) k 14.14k k 1.68M 18.34M 2.M 1 1 1k 1k 1k 1M 1M 1M 68

69 Method 3: Cf Design Ensure Good Phase Margin: 1.) Find f(aol=db) 2.) Set f(1/b zero) by choosing Cf: Good: Set f(1/b zero) = f(aol = db) for PM 45 degrees. Better: Set f(1/b zero) so f(cl) = ½ LowFrequency NG in db 12 1 f(aol = db) = 74.6kHz 1/B Zero Equation: 1 f(1/b zero)= 2 pi (R g R f ) C f Gain (db) f(aol = ½ DC NG) f(aol = db) f(cl_unmodified) k 14.14k k 1.68M 18.34M 2.M 1 1 1k 1k 1k 1M 1M 1M 69

70 Method 3: Cf Design Summary Summary: 1.) Ensure stability by placing: a) f(1/b zero) f(aol = db b) f(1/b pole) f(cl_unmodified) 2.) Try to adjust the zero location so the 1/B curve crosses the AOL curve in the middle of the 1/B span allowing for shifts in AOL Rg 4.99k Final Circuit V U1 OPA627E CLoad 1n V C1 27p Rf 1k Gain (db) Phase (degrees) PM = k 1.k 1.k 1.M 1.M 1.M 1k 1k 1k 1M 1M 1M 7

71 Method 4: NoiseGain Rg 4.99k Rf 1k Rn 75 V Cn 82n V U1 OPA627E CLoad 1n 71

72 Method 4: Noise Gain Results Theory: 1/Beta compensation. Raise highfrequency 1/Beta so the ROC occurs before the AOL pole causes the AOL slope to change Gain (db) Rg 4.9k Cn 82n Rn 75 Vfb L1 1T C4 1T Vin Rf 1k V V U1 OPA627E CLoad 1n AOL AOL*B 1/B 1/B Zero 1/B Pole AOL Pole ROC = 2dB/decade Phase (degrees) AOL*B Phase PM = k 1k 1k 1M 1M 1M 72

73 Method 4: Noise Gain Results When to use: Better for lighter capacitive loading When f(aol pole) < (Closed loop gain 2dB) Due to the increase in noise gain, this approach may not be practical when required noise gain is greater than the lowfrequency signal gain by more than ~253dB. 25m Rg 4.99k Rf 1k 2m Rn 75 Cn 82n V V U1 OPA627E CLoad 1n ltage (V) 15m 1m 5m 15u 3u 73 Time (seconds)

74 Method 4: Noise Gain Design Ensure Good Phase Margin: For 2dB/decade ROC, 1/Beta must intersect AOL above the AOL pole. Therefore: HighFreq NG > f(aol pole) f(1/b zero) < f(aol = HighFreq NG) f(aol pole) = 52.11dB f(aol pole) = 29.49kHz HighFreq NoiseGain Equation: R f HF NG = (R g R n ) 1/B Zero Equation: 1 f(1/b zero)= 2 pi R n C n Gain (db) f(aol pole) f(aol pole) 1/B Pole Equation: 1 f(1/b pole)= 2 pi (R n (R g R f ) C f k 14.14k k 1.68M 18.34M 2.M 1 1 1k 1k 1k 1M 1M 1M 74

75 Method 4: Noise Gain Design Ensure Good Phase Margin: 1.) Find f(aol pole) and f(aol pole) 2.) Set HighFreq NoiseGain by choosing Rn: Good: HF NG f(aol pole) Better: HF NG f(aol pole) 1dB 12 1 f(aol pole) = 52.11dB 8 f(aol pole) = 29.49kHz HighFreq NoiseGain Equation: R f HF NG = (R g R n ) Gain (db) f(aol pole) f(aol pole) k 14.14k k 1.68M 18.34M 2.M 1 1 1k 1k 1k 1M 1M 1M 75

76 Method 4: Noise Gain Design Ensure Good Phase Margin: 3.) Find f(cl_modified) = HF NG ) 4.) Set f(1/b zero) by choosing Cn: Good: f(1/b zero) f(cl_modified) Better: f(1/b zero) f(cl_modified) / 3.5 (~ ½ decade) 12 f(cl_modified) = 29.49kHz 1 8 f(cl_modified) HighFreq NoiseGain Equation: R f HF NG = (R g R n ) Gain (db) f(aol pole) f(aol pole) k 14.14k k 1.68M 18.34M 2.M 1 1 1k 1k 1k 1M 1M 1M 76

77 Method 4: Noise Gain Summary Summary: 1.) Ensure stability by setting: a) HF NG ( f(aol pole) 1dB) b) f(1/b zero) f(cl_modified) / 3.5 Rg 4.99k Rn 75 Cn 82n Final Circuit Rf 1k V V U1 OPA627E CLoad 1n Gain (db) Phase (degrees) PM = k 1.k 1.k 1.M 1.M 1.M 1 1k 1k 1k 1M 1M 1M 77

78 Method 4: Noise Gain Quick reminder that inverting and noninverting noise gain circuits are different! 25m Rg 4.99k Rf 1k 2m Rn 75 Cn 82n V U1 OPA627E CLoad 1n V ltage (V) 15m 1m 5m 1m. 15u 15.u 3u 3.u Time (seconds) Rg 4.99k Rf 1k 4m Rn 75 Cn 82n V V U1 OPA627E CLoad 1n ltage (V) 9m 14m 19m 24m 15u 78 3u Time (seconds). 15.u 3.u

79 Circuits with High Feedback Network Impedance 79

80 Circuits with High Feedback Network Impedance Rg 499k Rf 499k V Cstray 2p Vin U1 OPA627E 1 V (V) 1 1m Vin (V) 15u 3u Time (seconds). 15.u 3.u 8

81 Circuits with High Feedback Network Impedance Determine the issue: Rg 499k Cin 27p Zero in 1/Beta!! ROC = 4dB/decade!! Phase Margin 2!! Vfb L1 1T C1 1T Vin Rf 499k V Gain (db) U1 OPA627E AOL AOL*B 1/B ROC = 4dB/decade! 1/B Zero V Phase (degrees) AOL*B Phase PM = k 1k 1k 1M 1M 1M 81

82 Circuits with High Feedback Network Impedance Theory Rg 499k Cin 27p Vfb L1 1T C1 1T Rf 499k Vin V U1 OPA627E AOL Ro 54 Rf 499k Loaded AOL V Rg 499k Beta Cin 27p C1 AOL 1M Ro 54 Rf 499k Loaded AOL Beta Rg 499k Cin 27p 82

83 Circuits with High Feedback Network Impedance Theory Ro 54 Rf 499k Rg 499k AOL Load Beta Cin 27p Gain (db) Beta AOL Load Pole in Beta = Zero in 1/Beta AOL Unaffected Beta Pole & 1/Beta Zero Equation: 1 f(b pole)=f(1/b zero)= 2 pi (R g R f ) C in Phase (degrees) k 1.k 1k 1.k 1k 1.k 1M 1.M 1M 1.M 1M 1.M 83

84 Stabilize Circuits With High Feedback Network Impedance 84

85 Stability Options Zero in 1/Beta 12 The only practical option is to add a pole to cancel the 1/Beta Zero 1 8 Gain (db) k 1k 1k 1M 1M 1M k 1.k 1.k 1.M 1.M 1.M 85

86 Method 1: Cf Cf 21p Rg 499k Rf 499k V Cstray 2p U1 OPA627E V 86

87 Method 1: Cf Results Theory: 1/Beta compensation. Cf feedback places a pole in 1/Beta to cancel the zero from the input capacitance. 12 Vfb Rg 499k L1 1T C1 1T Cin 27p Cf 21p Rf 499k Vin V V U1 OPA627E Gain (db) Phase (degrees) AOL AOL*B 1/B AOL*B Phase 1/B Zero 1/B Pole ROC = 2dB/decade! PM = k 1k 1k 1M 1M 1M 87

88 Method 1: Cf Results When to use: Almost always a safe design practice. Limits gain at 1/(2*pi*Rf*Cf) Cf 21p 25m Rg 499k Rf 499k V (V) Cstray 2p U1 OPA627E 1m V Vin (V) 15u 3u Time (seconds) 88

89 Method 1: Cf Design Ensure Good Phase Margin: For 2dB/decade ROC, the 1/Beta pole must flatten the 1/Beta Zero before f(cl) Therefore f(1/beta pole) f(cl) 12 f(cl) = 445.6kHz 1/B Pole Equation: 1 f(1/b pole)= 2 pi R f C f 1/B Zero Equation: 1 f(1/b zero)= 2 pi (R g R f ) C in Gain (db) f(cl) k 1k 1k 1M 1M 1M k 1.k 1.k 1.M 1.M 1.M 89

90 Method 1: Cf Design Ensure Good Phase Margin: 1.) Find f(cl) 2.) Set f(1/b pole) by setting Cf: Good: f(1/b pole) f(cl) Better: f(1/b pole) f(cl)/ 3.5 (~ ½ decade) /B Pole Equation: 6 1 f(1/b pole)= 2 pi R 4 f C f 2 1/B Zero Equation: 1 f(1/b zero)= 2 pi (R g R f ) C in 2 4 Gain (db) f(cl) k 1k 1k 1M 1M 1M k 1.k 1.k 1.M 1.M 1.M

91 Method 1: Cf Summary Summary: 1.) Ensure stability by setting f(1/b pole) f(cl)/ 3.5 (~ ½ decade) 12 1 Rg 499k Cstray 2p Cf 21p Rf 499k V U1 OPA627E Gain (db) V Phase (degrees) PM = k 1k 1k 1M 1M 1M 91

92 Ro vs. Zo 92

93 When Ro is really Zo!! V V 4 2 s 8.432u U1 OPA627E V IG1 s uV 3 1 U1 OPA V IG1 93

94 With Complex Zo, Accurate Models are Key! Vin 6m 4 3 V 2 1 U1 OPA V CLoad 1uF Gain (db) AOL AOL*B 1/B ROC = 6dB/decade! (V) Vin (V) 4m 2m Phase (degrees) AOL*B Phase PM = 77!! k 1k 1k 1M 1M 1M 15u 3u Time (seconds) 94

95 With Complex Zo, Accurate Models are Key! 4 2 s uV 3 1 U1 OPA IG1 V 1k V Impedance (Ohms) 1k m k 1k 1k 1M 1M 1M 95

96 Questions/Comments? Thank you!! Special Thanks to: Art Kay Bruce Trump Marek Lis Tim Green PA Apps Team 96