CAV24C32. EEPROM Serial 32-Kb I 2 C - Automotive Grade 1

Transcription

1 V2432 EEPROM erial 32-b I 2 - utomotive Grade 1 Description he V2432 is a EEPROM erial 32 b I 2 devices, internally organized as 4096 words of 8 bits each. It features a 32 byte page write buffer and supports the tandard (100 khz) and Fast (400 khz) I 2 protocol. External address pins make it possible to address up to eight V2432 devices on the same bus. Features utomotive emperature Grade 1 ( 40 to +125 ) upports tandard and Fast I 2 Protocol 2.5 V to 5.5 V upply Voltage Range 32 Byte Page Write Buffer Hardware Write Protection for Entire Memory V Prefix for utomotive and Other pplications Requiring ite and hange ontrol chmitt riggers and Noise uppression Filters on I 2 Bus Inputs (L and D) Low Power MO echnology 1,000,000 Program/Erase ycles 100 Year Data Retention OI, OP 8 lead, and WLP 4 Ball and 5 Ball Packages his Device is Pb Free, Halogen Free/BFR Free, and RoH ompliant V WLP5 5 UFFIX E 567JQ WLP4 4 UFFIX E 567JY OP 8 Y UFFIX E 948L OI 8 W UFFIX E 751BD PIN ONFIGURION (op Views) 1 V L 2 V D WLP4 (4) B V WP D V WP V L WLP5 (5) B L 2 V L D 2, 1, 0 WP V2432 D OI (W), OP (Y) For the location of Pin 1, please consult the corresponding package drawing. PIN FUNION V Figure 1. Functional ymbol Pin Name 0, 1, 2 D L WP V V Function Device ddress Input erial Data Input/Output erial lock Input Write Protect Input Power upply Ground his document contains information on some products that are still under development. ON emiconductor reserves the right to change or discontinue these products without notice. ORDERING INFORMION ee detailed ordering and shipping information in the package dimensions section on page 8 of this data sheet. emiconductor omponents Industries, LL, 2017 May, 2018 Rev. 4 1 Publication Order Number: V2432/D

2 V2432 (OP 8) DEVIE MRING (OI 8) 32F YMXXX 32F = pecific Device ode = ssembly Location Y = Production Year (Last Digit) M = Production Month (1-9, O, N, D) XXX = Last hree Digits of ssembly Lot Number = Pb Free Package (WLP 5) 2 YW 2432F YMXXX 2432F = pecific Device ode = ssembly Location Y = Production Year (Last Digit) M = Production Month (1-9, O, N, D) XXX = Last hree Digits of ssembly Lot Number = Pb Free Package (WLP 4) B YW 2 = pecific Device ode Y = Production Year ode W = Production Workweek ode B Y W = pecific Device ode = Production Year ode = Production Workweek ode able 1. BOLUE MXIMUM RING Parameters Ratings Units torage emperature 65 to +150 Voltage on any Pin with Respect to Ground (Note 1) 0.5 to +6.5 V tresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality should not be assumed, damage may occur and reliability may be affected. 1. During input transitions, voltage undershoot on any pin should not exceed 1 V for more than 20 ns. Voltage overshoot on pins 0, 1, 2 and WP should not exceed V + 1 V for more than 20 ns, while voltage on the I 2 bus pins, L and D, should not exceed the absolute maximum ratings, irrespective of V. able 2. RELIBILIY HRERII (Note 2) ymbol Parameter Min Units N END (Note 3) Endurance 1,000,000 Program/Erase ycles DR Data Retention 100 Years 2. hese parameters are tested initially and after a design or process change that affects the parameter according to appropriate E Q100 and JEDE test methods. 3. Page Mode, V = 5 V, 25. able 3. D.. OPERING HRERII (V = 2.5 V to 5.5 V, = 40 to +125, unless otherwise specified.) ymbol Parameter est onditions Min Max Units I R Read urrent Read, f L = 400 khz 1 m I W Write urrent Write, f L = 400 khz 2 m I B tandby urrent ll I/O Pins at GND or V = 40 to I L I/O Pin Leakage Pin at GND or V 2 V IL Input Low Voltage x V V V IH Input High Voltage 0, 1, 2 and WP 0.7 x V V V L and D 0.7 x V 5.5 V OL Output Low Voltage V > 2.5 V, I OL = 3 m 0.4 V Product parametric performance is indicated in the Electrical haracteristics for the listed test conditions, unless otherwise noted. Product performance may not be indicated by the Electrical haracteristics if operated under different conditions. 2

3 V2432 able 4. PIN IMPEDNE HRERII (V = 2.5 V to 5.5 V, = 40 to +125, unless otherwise specified.) ymbol Parameter onditions Max Units IN (Note 4) D I/O Pin apacitance V IN = 0 V, = 25, V = 5.0 V 8 pf IN (Note 4) Input apacitance (other pins) V IN = 0 V, = 25, V = 5.0 V 6 pf I WP (Note 5) WP Input urrent V IN < V IH, V = 5.5 V 130 I (Note 5) ddress Input urrent (0, 1, 2) Product Rev F V IN < V IH, V = 3.3 V 120 V IN < V IH, V = 2.5 V 80 V IN < V IH 2 V IN < V IH, V = 5.5 V 50 V IN < V IH, V = 3.3 V 35 V IN < V IH, V = 2.5 V 25 V IN > V IH 2 4. hese parameters are tested initially and after a design or process change that affects the parameter according to appropriate E Q100 and JEDE test methods. 5. When not driven, the WP, 0, 1 and 2 pins are pulled down to GND internally. For improved noise immunity, the internal pull down is relatively strong; therefore the external driver must be able to supply the pull down current when attempting to drive the input HIGH. o conserve power, as the input level exceeds the trip point of the MO input buffer (~ 0.5 x V ), the strong pull down reverts to a weak current source. able 5... HRERII (V = 2.5 V to 5.5 V, = 40 to +125, unless otherwise specified.) (Note 6) ymbol Parameter tandard Fast Min Max Min Max F L lock Frequency khz t HD: R ondition Hold ime s t LOW Low Period of L lock s t HIGH High Period of L lock s t U: R ondition etup ime s t HD:D Data In Hold ime 0 0 s t U:D Data In etup ime ns t R D and L Rise ime ns t F (Note 6) D and L Fall ime ns t U:O OP ondition etup ime s t BUF Bus Free ime Between OP and R s t L Low to Data Out Valid s t DH Data Out Hold ime ns i (Note 6) Noise Pulse Filtered at L and D Inputs ns t U:WP WP etup ime 0 0 s t HD:WP WP Hold ime s t WR Write ycle ime 5 5 ms t PU (Notes 7, 8) Power up to Ready Mode 1 1 ms 6. est conditions according to est onditions table. 7. ested initially and after a design or process change that affects this parameter. 8. t PU is the delay between the time V is stable and the device is ready to accept commands. able 6... E ONDIION Input Drive Levels Input Rise and Fall ime Input Reference Levels Output Reference Level Output est Load 0.2 x V to 0.8 x V 50 ns 0.3 x V, 0.7 x V 0.5 x V urrent ource I OL = 3 m; L = 100 pf Units 3

4 V2432 Power-On Reset (POR) Each V2432 incorporates Power-On Reset (POR) circuitry which protects the internal logic against powering up in the wrong state. he device will power up into tandby mode after V exceeds the POR trigger level and will power down into Reset mode when V drops below the POR trigger level. his bi-directional POR behavior protects the device against brown-out failure following a temporary loss of power. Pin Description L: he erial lock input pin accepts the clock signal generated by the Master. D: he erial Data I/O pin accepts input data and delivers output data. In transmit mode, this pin is open drain. Data is acquired on the positive edge, and is delivered on the negative edge of L. 0, 1 and 2 : he ddress inputs set the device address that must be matched by the corresponding lave address bits. he ddress inputs are hard-wired HIGH or LOW allowing for up to eight devices to be used (cascaded) on the same bus. When left floating, these pins are pulled LOW internally. WP: When pulled HIGH, the Write Protect input pin inhibits all write operations. When left floating, this pin is pulled LOW internally. Functional Description he V2432 supports the Inter-Integrated ircuit (I 2 ) Bus protocol. he protocol relies on the use of a Master device, which provides the clock and directs bus traffic, and lave devices which execute requests. he V2432 operates as a lave device. Both Master and lave can transmit or receive, but only the Master can assign those roles. I 2 Bus Protocol he 2-wire I 2 bus consists of two lines, L and D, connected to the V supply via pull-up resistors. he Master provides the clock to the L line, and either the Master or the laves drive the D line. 0 is transmitted by pulling a line LOW and a 1 by letting it stay HIGH. Data transfer may be initiated only when the bus is not busy (see.. haracteristics). During data transfer, D must remain stable while L is HIGH. R/OP ondition n D transition while L is HIGH creates a R or OP condition (Figure 2). he R consists of a HIGH to LOW D transition, while L is HIGH. bsent the R, a lave will not respond to the Master. he OP completes all commands, and consists of a LOW to HIGH D transition, while L is HIGH. Device ddressing he Master addresses a lave by creating a R condition and then broadcasting an 8-bit lave address. For the V2432, the first four bits of the lave address are set to 1010 (h); the next three bits, 2, 1 and 0, must match the logic state of the similarly named input pins. he R/W bit tells the lave whether the Master intends to read (1) or write (0) data (Figure 3). cknowledge During the 9 th clock cycle following every byte sent to the bus, the transmitter releases the D line, allowing the receiver to respond. he receiver then either acknowledges () by pulling D LOW, or does not acknowledge (No) by letting D stay HIGH (Figure 4). Bus timing is illustrated in Figure 5. L D R ONDIION Figure 2. tart/top iming OP ONDIION R/W DEVIE DDRE Figure 3. lave ddress Bits 4

5 V2432 BU RELEE DELY (RNMIER) BU RELEE DELY (REEIVER) L FROM MER D OUPU FROM RNMIER D OUPU FROM REEIVER R DELY ( t ) Figure 4. cknowledge iming EUP ( t U:D ) t F t HIGH t R t LOW t LOW L t U: t HD:D t HD:D t U:D t U:O D IN t t DH t BUF D OU Figure 5. Bus iming WRIE OPERION Byte Write o write data to memory, the Master creates a R condition on the bus and then broadcasts a lave address with the R/W bit set to 0. he Master then sends two address bytes and a data byte and concludes the session by creating a OP condition on the bus. he lave responds with after every byte sent by the Master (Figure 6). he OP starts the internal Write cycle, and while this operation is in progress (t WR ), the D output is tri-stated and the lave does not acknowledge the Master (Figure 7). Page Write he Byte Write operation can be expanded to Page Write, by sending more than one data byte to the lave before issuing the OP condition (Figure 8). Up to 32 distinct data bytes can be loaded into the internal Page Write Buffer starting at the address provided by the Master. he page address is latched, and as long as the Master keeps sending data, the internal byte address is incremented up to the end of page, where it then wraps around (within the page). New data can therefore replace data loaded earlier. Following the OP, data loaded during the Page Write session will be written to memory in a single internal Write cycle (t WR ). cknowledge Polling s soon (and as long) as internal Write is in progress, the lave will not acknowledge the Master. his feature enables the Master to immediately follow-up with a new Read or Write request, rather than wait for the maximum specified Write time (t WR ) to elapse. Upon receiving a No response from the lave, the Master simply repeats the request until the lave responds with. Hardware Write Protection With the WP pin held HIGH, the entire memory is protected against Write operations. If the WP pin is left floating or is grounded, it has no impact on the Write operation. he state of the WP pin is strobed on the last falling edge of L immediately preceding the 1 st data byte (Figure 9). If the WP pin is HIGH during the strobe interval, the lave will not acknowledge the data byte and the Write request will be rejected. Delivery tate he V2432 is shipped erased, i.e., all bytes are FFh. 5

6 V2432 BU IVIY: MER R LVE LVE DDRE *a 15 a 12 are don t care bits DDRE DDRE * * * * Figure 6. Byte Write equence D a 15 a 8 a 7 a 0 d 7 d 0 O P P L D 8th Bit Byte n t WR OP ONDIION R ONDIION DDRE Figure 7. Write ycle iming BU IVIY: MER R LVE DDRE DDRE DDRE D n D n+1 D n+p O P P LVE n = 1 P 31 Figure 8. Page Write equence DDRE D L D a 7 a 0 d 7 d 0 t U:WP WP t HD:WP Figure 9. WP iming 6

7 V2432 RED OPERION Immediate Read o read data from memory, the Master creates a R condition on the bus and then broadcasts a lave address with the R/W bit set to 1. he lave responds with and starts shifting out data residing at the current address. fter receiving the data, the Master responds with No and terminates the session by creating a OP condition on the bus (Figure 10). he lave then returns to tandby mode. elective Read o read data residing at a specific address, the selected address must first be loaded into the internal address register. his is done by starting a Byte Write sequence, whereby the Master creates a R condition, then broadcasts a lave address with the R/W bit set to 0 and then sends two address bytes to the lave. Rather than completing the Byte Write sequence by sending data, the Master then creates a R condition and broadcasts a lave address with the R/W bit set to 1. he lave responds with after every byte sent by the Master and then sends out data residing at the selected address. fter receiving the data, the Master responds with No and then terminates the session by creating a OP condition on the bus (Figure 11). equential Read If, after receiving data sent by the lave, the Master responds with, then the lave will continue transmitting until the Master responds with No followed by OP (Figure 12). During equential Read the internal byte address is automatically incremented up to the end of memory, where it then wraps around to the beginning of memory. BU IVIY MER R LVE DDRE N O OP P LVE D L 8 9 D 8th Bit D OU NO Figure 10. Immediate Read equence and iming OP BU IVIY: MER R LVE DDRE DDRE DDRE R LVE DDRE N O O P P LVE D Figure 11. elective Read equence BU IVIY: MER LVE DDRE N O O P P LVE D n D n+1 D n+2 D n+x Figure 12. equential Read equence 7

8 V2432 ORDERING INFORMION Device Order Number V24325R (Note 10) pecific Device Marking Package ype Lead Finish hipping 2 WLP5 ngu ape & Reel, 5,000 Units / Reel V24325R (Note 10) P WLP5 with Die oat ngu ape & Reel, 5,000 Units / Reel V24324R (Note 10) B WLP4 with Die oat ngu ape & Reel, 5,000 Units / Reel V2432WE G3 2432F OI 8, JEDE NiPdu ape & Reel, 3,000 Units / Reel V2432YE G (Note 10) 32F OP 8 NiPdu ube, 100 Units / ube V2432YE G3 32F OP 8 NiPdu ape & Reel, 3,000 Units / Reel For information on tape and reel specifications, including part orientation and tape sizes, please refer to our ape and Reel Packaging pecifications Brochure, BRD8011/D. 9. ll packages are RoH compliant (Lead free, Halogen free). 10. Please contact your nearest ON emiconductor ales office for availability. 11. aution: he EEPROM devices delivered in WLP must never be exposed to ultraviolet light. When exposed to ultraviolet light the EEPROM cells lose their stored data. ON emiconductor is licensed by the Philips orporation to carry the I 2 bus protocol. 8

9 MEHNIL E OULINE PGE DIMENION OI 8, 150 mils E 751BD 01 IUE O DE 19 DE 2008 YMBOL MIN NOM MX b E1 E c D E E e 1.27 B h PIN # 1 IDENIFIION L θ 0º 8º OP VIEW D h 1 θ c e b L IDE VIEW END VIEW Notes: (1) ll dimensions are in millimeters. ngles in degrees. (2) omplies with JEDE M-012. DOUMEN NUMBER: U: REFERENE: emiconductor omponents Industries, LL, 2002 October, 2002 Rev. 0 DERIPION: 98ON34272E ON EMIONDUOR NDRD OI 8, 150 MIL 1 Electronic versions are uncontrolled except when accessed directly from the Document Repository. Printed versions are uncontrolled except when stamped ONROLLED OPY in red. ase Outline Number: PGE 1 OF XXX 2

10 DOUMEN NUMBER: 98ON34272E PGE 2 OF 2 IUE REVIION DE O RELEED FOR PRODUION FROM POD #OI O ON 19 DE 2008 EMIONDUOR. REQ. BY B. BERGMN. ON emiconductor and are registered trademarks of emiconductor omponents Industries, LL (ILL). ILL reserves the right to make changes without further notice to any products herein. ILL makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does ILL assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. ypical parameters which may be provided in ILL data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. ll operating parameters, including ypicals must be validated for each customer application by customer s technical experts. ILL does not convey any license under its patent rights nor the rights of others. ILL products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the ILL product could create a situation where personal injury or death may occur. hould Buyer purchase or use ILL products for any such unintended or unauthorized application, Buyer shall indemnify and hold ILL and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that ILL was negligent regarding the design or manufacture of the part. ILL is an Equal Opportunity/ffirmative ction Employer. his literature is subject to all applicable copyright laws and is not for resale in any manner. emiconductor omponents Industries, LL, 2008 December, 2008 Rev. 01O ase Outline Number: 751BD

11 MEHNIL E OULINE PGE DIMENION OP8, 4.4x3 E 948L 01 IUE O DE 19 DE 2008 b YMBOL MIN NOM MX b E1 E c D E E e 0.65 B L 1.00 REF L1 θ º 8º e OP VIEW D 2 1 c IDE VIEW 1 L1 END VIEW L Notes: (1) ll dimensions are in millimeters. ngles in degrees. (2) omplies with JEDE MO-153. DOUMEN NUMBER: U: REFERENE: emiconductor omponents Industries, LL, 2002 October, 2002 Rev. 0 DERIPION: 98ON34428E ON EMIONDUOR NDRD OP8, 4.4X3 1 Electronic versions are uncontrolled except when accessed directly from the Document Repository. Printed versions are uncontrolled except when stamped ONROLLED OPY in red. ase Outline Number: PGE 1 OF XXX 2

12 DOUMEN NUMBER: 98ON34428E PGE 2 OF 2 IUE REVIION DE O RELEED FOR PRODUION FROM POD #OP O ON 19 DE 2008 EMIONDUOR. REQ. BY B. BERGMN. ON emiconductor and are registered trademarks of emiconductor omponents Industries, LL (ILL). ILL reserves the right to make changes without further notice to any products herein. ILL makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does ILL assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. ypical parameters which may be provided in ILL data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. ll operating parameters, including ypicals must be validated for each customer application by customer s technical experts. ILL does not convey any license under its patent rights nor the rights of others. ILL products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the ILL product could create a situation where personal injury or death may occur. hould Buyer purchase or use ILL products for any such unintended or unauthorized application, Buyer shall indemnify and hold ILL and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that ILL was negligent regarding the design or manufacture of the part. ILL is an Equal Opportunity/ffirmative ction Employer. his literature is subject to all applicable copyright laws and is not for resale in any manner. emiconductor omponents Industries, LL, 2008 December, 2008 Rev. 01O ase Outline Number: 948L

13 MEHNIL E OULINE PGE DIMENION LE 4:1 WLP5, 1.34x0.91 E 567JQ IUE DE 09 JUN 2015 PIN 1 REFERENE 2X 2X NOE DEIL E OP VIEW 1 IDE VIEW B 2 D DIE O (OPIONL) EING PLNE DEIL 3 2 NOE: 1. DIMENIONING ND OLERNING PER ME Y14.5M, ONROLLING DIMENION: MILLIMEER. 3. OPLNRIY PPLIE O HE PHERIL ROWN OF HE OLDER BLL. 4. DIMENION b I MEURED HE MXIMUM BLL DIMEER PRLLEL O DUM. MILLIMEER DIM MIN MX REF REF b D 1.34 B E 0.91 B e 0.40 B e B GENERI MRING DIGRM* 5X b 0.05 B 0.03 e B BOOM VIEW e1 XYW X = pecific Device ode Y = Year W = Work Week *his information is generic. Please refer to device data sheet for actual part marking. Pb Free indicator, G or microdot, may or may not be present. REOMMENDED OLDERING FOOPRIN* 1 PGE OULINE 0.69 PIH 5X PIH DIMENION: MILLIMEER *For additional information on our Pb Free strategy and soldering details, please download the ON emiconductor oldering and Mounting echniques Reference Manual, OLDERRM/D. DOUMEN NUMBER: U: NEW NDRD: emiconductor omponents Industries, LL, 2002 October, 2002 Rev. 0 DERIPION: 98ON82067F ON EMIONDUOR NDRD WLP5, 1.34X Electronic versions are uncontrolled except when accessed directly from the Document Repository. Printed versions are uncontrolled except when stamped ONROLLED OPY in red. ase Outline Number: PGE 1 OF XXX 2

14 DOUMEN NUMBER: 98ON82067F PGE 2 OF 2 IUE REVIION DE O RELEED FOR PRODUION. REQ. BY I. MRINO. 04 FEB 2014 DDED BIDE OING OPION ND DEIL. REQ. BY B. BEER. 09 JUN 2015 ON emiconductor and are registered trademarks of emiconductor omponents Industries, LL (ILL). ILL reserves the right to make changes without further notice to any products herein. ILL makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does ILL assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. ypical parameters which may be provided in ILL data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. ll operating parameters, including ypicals must be validated for each customer application by customer s technical experts. ILL does not convey any license under its patent rights nor the rights of others. ILL products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the ILL product could create a situation where personal injury or death may occur. hould Buyer purchase or use ILL products for any such unintended or unauthorized application, Buyer shall indemnify and hold ILL and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that ILL was negligent regarding the design or manufacture of the part. ILL is an Equal Opportunity/ffirmative ction Employer. his literature is subject to all applicable copyright laws and is not for resale in any manner. emiconductor omponents Industries, LL, 2015 June, 2015 Rev. ase Outline Number: 568JQ

15 MEHNIL E OULINE PGE DIMENION LE 4:1 WLP4, 0.77x0.77 E 567JY IUE DE 07 MR 2017 NOE 5 PIN 1 REFERENE NOE 4 4X 0.05 b 0.05 B 0.03 DEIL B E OP VIEW IDE VIEW 1 2 e BOOM VIEW 2 e B D REOMMENDED OLDERING FOOPRIN* 1 PGE OULINE NOE 3 EING PLNE NOE 6 DIE O (OPIONL) DEIL 3 2 NOE: 1. DIMENIONING ND OLERNING PER ME Y14.5M, ONROLLING DIMENION: MILLIMEER. 3. DUM, HE EING PLNE, I DEFINED BY HE PHERIL ROWN OF HE OLDER BLL. 4. OPLNRIY PPLIE O PHERIL ROWN OF HE OLDER BLL. 5. DIMENION b I MEURED HE MXIMUM ON BLL DIMEER PRLLEL O DUM. 6. BIDE OING I OPIONL. MILLIMEER DIM MIN NOM MX REF REF b D E e 0.40 B GENERI MRING DIGRM* X Y W X YW = pecific Device ode = Year = Work Week *his information is generic. Please refer to device data sheet for actual part marking. Pb Free indicator, G or microdot, may or may not be present PIH 4X PIH DIMENION: MILLIMEER *For additional information on our Pb Free strategy and soldering details, please download the ON emiconductor oldering and Mounting echniques Reference Manual, OLDERRM/D. DOUMEN NUMBER: U: NEW NDRD: emiconductor omponents Industries, LL, 2002 October, 2002 Rev. 0 DERIPION: 98ON85186F ON EMIONDUOR NDRD WLP4, 0.77X Electronic versions are uncontrolled except when accessed directly from the Document Repository. Printed versions are uncontrolled except when stamped ONROLLED OPY in red. ase Outline Number: PGE 1 OF XXX 2

16 DOUMEN NUMBER: 98ON85186F PGE 2 OF 2 IUE REVIION DE O RELEED FOR PRODUION. REQ. BY I. MRINO. 06 MY 2014 ORREED DEIL ND DIMENION 1, DDED NOMINL VLUE. REQ. BY V. RIUNOIU. 23 JUN 2016 B MODIFIED DIMENION D ND E O 0.77X0.77. REQ. BY V. RIUNOIU. 02 UG 2016 MODIFIED DIMENION 1 ND 2 VLUE. REQ. BY V. RIUNOIU. 07 MR 2017 ON emiconductor and are registered trademarks of emiconductor omponents Industries, LL (ILL). ILL reserves the right to make changes without further notice to any products herein. ILL makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does ILL assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. ypical parameters which may be provided in ILL data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. ll operating parameters, including ypicals must be validated for each customer application by customer s technical experts. ILL does not convey any license under its patent rights nor the rights of others. ILL products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the ILL product could create a situation where personal injury or death may occur. hould Buyer purchase or use ILL products for any such unintended or unauthorized application, Buyer shall indemnify and hold ILL and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that ILL was negligent regarding the design or manufacture of the part. ILL is an Equal Opportunity/ffirmative ction Employer. his literature is subject to all applicable copyright laws and is not for resale in any manner. emiconductor omponents Industries, LL, 2017 March, 2017 Rev. ase Outline Number: 567JY

17 ON emiconductor and are trademarks of emiconductor omponents Industries, LL dba ON emiconductor or its subsidiaries in the United tates and/or other countries. ON emiconductor owns the rights to a number of patents, trademarks, copyrights, trade secrets, and other intellectual property. listing of ON emiconductor s product/patent coverage may be accessed at Marking.pdf. ON emiconductor reserves the right to make changes without further notice to any products herein. ON emiconductor makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does ON emiconductor assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. Buyer is responsible for its products and applications using ON emiconductor products, including compliance with all laws, regulations and safety requirements or standards, regardless of any support or applications information provided by ON emiconductor. ypical parameters which may be provided in ON emiconductor data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. ll operating parameters, including ypicals must be validated for each customer application by customer s technical experts. ON emiconductor does not convey any license under its patent rights nor the rights of others. ON emiconductor products are not designed, intended, or authorized for use as a critical component in life support systems or any FD lass 3 medical devices or medical devices with a same or similar classification in a foreign jurisdiction or any devices intended for implantation in the human body. hould Buyer purchase or use ON emiconductor products for any such unintended or unauthorized application, Buyer shall indemnify and hold ON emiconductor and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that ON emiconductor was negligent regarding the design or manufacture of the part. ON emiconductor is an Equal Opportunity/ffirmative ction Employer. his literature is subject to all applicable copyright laws and is not for resale in any manner. PUBLIION ORDERING INFORMION LIERURE FULFILLMEN: Literature Distribution enter for ON emiconductor E. 32nd Pkwy, urora, olorado U Phone: or oll Free U/anada Fax: or oll Free U/anada orderlit@onsemi.com N. merican echnical upport: oll Free U/anada Europe, Middle East and frica echnical upport: Phone: ON emiconductor Website: Order Literature: For additional information, please contact your local ales Representative