CS429: Computer Organization and Architecture

Transcription

1 CS429: Computer Organization and Architecture Warren Hunt, Jr. and Bill Young epartment of Computer Sciences University of Texas at Austin Last updated: November 5, 2014 at 11:25 CS429 Slideset 16: 1

2 Control Combinations Load/use ispredict Load Use JXX Combination A Combination B Two special cases can arise on the same clock cycle. Combination A: Not-taken branch instruction at branch target Combination B: Instruction that reads from memory to %esp Followed by instruction CS429 Slideset 16: 2

3 Control Combination A Load/use ispredict Load Use JXX Combination A Combination B Condition F W Processing stall normal normal normal ispredicted normal normal normal Branch Combination stall normal normal Should handle as mispredicted branch. Stalls F pipeline register. But PC selection logic will be using _val anyway. CS429 Slideset 16: 3

4 Control Combination B: First Attempt Load/use ispredict Load Use JXX Combination A Combination B Condition F W Processing stall normal normal normal Load/Use Hazard stall stall normal normal Combination stall normal normal + stall Would attempt to and stall pipeline register. Signalled by processor as pipeline error. CS429 Slideset 16: 4

5 Control Combination B: Correct Approach Load/use ispredict Load Use JXX Combination A Combination B Condition F W Processing stall normal normal normal Load/Use Hazard stall stall normal normal Combination stall stall normal normal Load / use hazard should get priority. instruction should be held in decode stage for additional cycle. CS429 Slideset 16: 5

6 Corrected Pipeline Control Logic Condition F W Processing stall normal normal normal Load/Use Hazard stall stall normal normal Combination stall stall normal normal Load / use hazard should get priority. instruction should be held in decode stage for additional cycle. CS429 Slideset 16: 6

7 Pipeline Summary ata Hazards ost handled by forwarding with no performance penalty Load / use hazard requires one cycle stall Control Hazards Cancel instructions when detect mispredicted branch; two cycles wasted Stall fetch stage while pass through pipeline; three cycles wasted. Control Combinations ust analyze carefully First version had a subtle bug Only arises with unusual instruction combination CS429 Slideset 16: 7

8 Performance Analysis with Pipelining CPU time = Seconds Program = Instructions Program Cycles Instruction Seconds Cycle Ideal pipelined machine: CPI = 1 One instruction completed per cycle. But much faster cycle time than unpipelined machine. However, hazards work against the ideal Hazards resolved using forwarding are fine. Stalling degrades performance and instruction completion rate is interrupted. CPI is a measure of the architectural efficiency of the design. CS429 Slideset 16: 8

9 Computing CPI CPI is a function of useful instructions and s: CPI = C i + C b C i = C b C i You can reformulate this to account for: load penalties (lp) branch misprediction penalties (mp) urn penalties (rp) CPI = lp + mp + rp CS429 Slideset 16: 9

10 Computing CPI (2) So, how do we determine the penalties? epends on how often each situation occurs on average. How often does a load occur and how often does that load cause a stall? How often does a branch occur and how often is it mispredicted? How often does a urn occur? We can measure these using: a simulator, or hardware performance counters. We can also estimate them through historical averages. Then use estimates to make early design tradeoffs for the architecture. CS429 Slideset 16: 10

11 Computing CPI (3) Cause Name Instruction Condition Stalls Product Frequency Frequency Load/use lp ispredict mp Return rp Total penalty 0.31 This is not ideal. This gets worse when: CPI = = 1.31 == 31% you also account for non-ideal memory access latency; deeper pipeline (where stalls per hazard increase). CS429 Slideset 16: 11