MEMORY SYSTEM. Mahdi Nazm Bojnordi. CS/ECE 3810: Computer Organization. Assistant Professor School of Computing University of Utah

Transcription

1 MEMORY SYSTEM Mahdi Nazm Bojnordi Assistant Professor School of Computing University of Utah CS/ECE 3810: Computer Organization

2 Overview Notes Homework 9 (deadline Apr. 9 th ) n Verify your submitted file before midnight This lecture Pipeline hazards n Control Memory system n Cache

3 Recall: Pipeline Hazards Structural hazards: multiple instructions compete for the same resource Data hazards: a dependent instruction cannot proceed because it needs a value that hasn t been produced Control hazards: the next instruction cannot be fetched because the outcome of an earlier branch is unknown

4 Control Hazards Sample C++ code for (i=100; i!= 0; i--) { sum = sum + i; } total = total + sum; How many branches in this code?

5 Control Hazards Sample C++ code for (i=100; i!= 0; i--) { sum = sum + i; } total = total + sum; addi $1, $0, 100 for: beq $0, $1, next next: add $2, $2, $1 addi $1, $1, -1 J for add $3, $3, $2 What are possible target instructions?

6 Control Hazards Sample C++ code for (i=100; i!= 0; i--) { sum = sum + i; } total = total + sum; addi $1, $0, 100 for: beq $0, $1, next add $2, $2, $1 addi $1, $1, -1 J for ALU next: add $3, $3, $2 What happens inside the pipeline?

7 Control Hazards The outcome of the branch

8 Handling Control Hazards 1. introducing stall cycles and delay slots How many cycles/slots? One branch per every six instructions on average!! addi $1, $0, 100 for: beq $0, $1, next nothing nothing add $2, $2, $1 ALU addi $1, $1, -1 J for 2 additional delay slots per 6 cycles!

9 Handling Control Hazards 1. introducing stall cycles and delay slots How many cycles/slots? One branch per every six instructions on average!! addi $1, $0, 100 for: beq $0, $1, next nothing add $2, $2, $1 addi $1, $1, -1 ALU J for nothing 1 additional delay slot, but longer path

10 Handling Control Hazards 1. introducing stall cycles and delay slots How many cycles/slots? One branch per every six instructions on average!! addi $1, $0, 100 for: beq $0, $1, next nothing add $2, $2, $1 J for ALU next: addi $1, $1, -1 add r3, r3, r2 Reordering instructions may help

11 Handling Control Hazards Strategies for filling up the branch delay slot (a) is the best choice; what about (b) and (c)?

12 Handling Control Hazards 1. introducing stall cycles and delay slots How many cycles/slots? One branch per every six instructions on average!! addi $1, $0, 100 for: beq $0, $1, next nothing add $2, $2, $1 J for ALU next: addi $1, $1, -1 add r3, r3, r2 Jump and function calls can be resolved in the decode stage.

13 Handling Control Hazards 1. introducing stall cycles and delay slots 2. predict the branch outcome n simply assume the branch is taken or not taken n predict the next PC addi $1, $0, 100 for: beq $0, $1, next add $2, $2, $1 addi $1, $1, -1 J for ALU next: add r3, r3, r2 May need to cancel the wrong path

14 Handling Control Hazards Pipeline without branch predictor PC IF (br) PC + 4 Read Compare Br-target

15 Handling Control Hazards Pipeline with branch predictor PC IF (br) Branch Predictor PC + 4 Read Compare Br-target

16 Handling Control Hazards The 2-bit branch predictor

17 Summary of the Pipeline

18 Memory System Data and instructions are stored on DRAM chips DRAM has high bit density and low speed An access DRAM may take about 300 processor cycles How to bridge the speed gap? Processor Memory ~300X

19 Memory Hierarchy The basic structure of a memory hierarchy. isters 1KB 1 cycle L1 data or instruction Cache 32KB 2 cycles L2 cache 2MB 15 cycles Memory 1GB 300 cycles Disk 80 GB 10M cycles

20 Memory Hierarchy The basic structure of a memory hierarchy. Multiple levels of the memory Idea: keep important data closer to processor. Upper Level Lower Level

21 Cache Architecture Design principles Temporal locality: if you used some data recently, you will likely use it again Spatial locality: if you used some data recently, you will likely access its neighbors Cache terminology Access time Hit vs. miss Miss penalty Processor Cache Memory

22 Direct-Mapped Cache Cache address

23 Direct-Mapped Cache Cache lookup