Hardware-Software Cosynthesis of Multi-Mode Multi-Task Embedded Systems with Real-Time Constraints

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1 Hardware-Software Cosyntess of Mult-Mode Mult-Task Embedded Systems wt Real-Tme Constrants Hyunok O Soono Ha Te Scool of Electrcal Engneerng and Computer Scence Seoul Natonal Unversty Seoul , KOREA TEL : {oo,sa}@comp.snu.ac.kr ABSTRACT An embedded system s called mult-mode wen t supports multple applcatons by dynamcally reconfgurng te system functonalty. Ts paper proposes a ardware-software cosyntess tecnque for mult-mode mult-task embedded systems wt real-tme constrants. Te cosyntess problem nvolves tree subproblems: selecton of approprate processng elements, mappng and scedulng of functon modules to te selected processng elements, and scedule analyss. Te proposed cosyntess framework defnes an teraton loop of tree steps tat solve te subproblems separately. One of te key benefts of suc a modular approac s extensblty and adaptablty. Moreover, unlke te prevous approaces, te proposed tecnque consders task sarng between modes and ardware sarng between tasks at te same tme. We demonstrate te usefulness of te proposed tecnque wt a realstc multmode embedded system tat supports tree modes of operaton wt 5 dfferent tasks. Keywords Hardware-software cosyntess, mult-mode, mult-task 1. Introducton An embedded system s called mult-mode wen t supports multple applcatons by dynamcally reconfgurng te system functonalty. Suc reconfgurablty s desrable to cope wt rapdly evolvng standards and sgnal processng algortms as well as to enance te ardware utlzaton sgnfcantly. A multmode moble termnal, for example, can be used for a PCS pone, MP3 player, and VOD termnal, by manually selectng te mode. We assume tat an applcaton defnes a mode of te system and te system runs a sngle applcaton at a tme. A sngle mode, n general, s a real-tme mult-task system meanng tat eac applcaton conssts of a set of real-tme tasks tat sould be sceduled wtn tme constrants. Terefore, a crtcal desgn constrant of a mult-mode mult-task embedded system s to make all applcatons scedulable. Volaton of ts scedulablty constrant can be detected usng te scedulablty tests applcable for real-tme scedulng tecnques[1][2]. Te man focus of ts paper s to fnd a mnmum-cost system arctecture tat satsfes te scedulablty constrants, gven a real-tme scedulng tecnque. We assume tat a task s specfed as an acyclc grap of wc a node represents a functon module suc as DCT(Dscrete Cosne Transform), MC (Moton Compensaton), and so on. And tere s a lbrary of canddate processng elements, processors and IP blocks, wt gven tmng nformaton for eac functon module: ow long t takes for eac processng element(pe) to execute te functon. A ardware mplementaton of a module may also be regarded as a processng element wc takes nfnte amount of tme for oter functon modules. Ten, te problem becomes selectng te approprate processng elements and mappng functon modules to te selected processng elements. We defne ts problem as te HW/SW cosyntess problem. Wle tere ave been some researc efforts for cosyntess of mult-task systems[3][4], only a few researc results exst for mult-mode mult-task systems[5]. A nave approac of applyng te cosyntess tecnques of mult-task systems drectly to eac mode separately s not optmal f a task s common n multple modes. Terefore, te approac proposed n [5] consders te task sarng effect. Gven task sets and processng elements, tey examne te scedulablty of eac mode assumng tat all tasks are run n a processor. If te scedulablty constrant s volated, tey sngle out te best task and te amount of executon tme to be reduced to make all modes scedulable. Tey reduce te task executon tme by mplementng some code fragments to ardware component. However, tey do not consder te resource sarng possblty between tasks so tat tey determne te best functon module for ardware mplementaton separately for eac selected task. 1 Compared wt ts prevous approac, te proposed tecnque dffers n two aspects. We address two ssues at te same tme: wc processng elements to coose and wc functonal module to mplement n ardware. Second, we consder te possblty of ardware resource sarng between tasks. Ts researc s supported by Natonal Researc Laboratory Program (number M ). Ts work s sponsored by Bran Korea 21 project. Te RIACT at Seoul Natonal Unversty provdes researc facltes for ts study.

2 Te rest of te paper s organzed as follows. In te next secton, we state te problem and assumptons more clearly and present an example mult-mode mult-task system, expermented n ts paper. Secton 3 presents te structure of te proposed cosyntess framework and secton 4 explans te proposed algortm n detal. And some expermental results are sown n secton 5. We draw concluson n secton Prelmnares In ts secton, we defne some notatons and termnologes and state te cosyntess problem clearly wt an example mult-mode system A mult-mode system Π conssts of a fxed number of modes {Π } or Π={Π 1, Π 2, Π 3, }. Eac mode Π ncludes a number of tasks {τ j } and eac task τ j s composed of modules {m k } tat are functonal blocks. Te perod T j and deadlne D j of eac task τ j are defned separately for eac mode Π. In case of a sporadc task, T j may be set as te mnmum nter-arrval tme between successve requests. We are also gven a lbrary of canddate processng elements (PE's) {p m } tat ncludes mcroprocessors, IPs, and ASIC core mplementatons of functon modules. For eac processng element p m, ts cost c m and te worst case executon tme t m,k of module m k on p m are assumed to be gven for eac module. Ten, te cosyntess problem s to select a set of processng elements, PE={p n }, and to fnd a mappng φ:{m k }Æ{p n } and scedulng of tasks {τ j } to mnmze te total cost of processng elements wle satsfyng te scedulablty condton. Dependng on wc real-tme scedulng tecnque s used, we use te approprate scedulablty test. We let sl(τ j,pe) be te scedule lengt of task τ j on te selected processng elements. Ten, te utlzaton of mode Π, (PE), becomes U Π sl( τ j, P) U Π ( P) = (1) T τ j j For nstance, f a rate-monotonc scedulng tecnque s adopted, te scedulablty test compares ts utlzaton value wt 1 n(2 n 1) were n s te number of tasks[1]. Fgure 1 sows a real-lfe example of mult-mode embedded system expermented n ts paper. Te system supports 3 dfferent modes of operaton: vdeo pone (Π 1 ), vdeo player (Π 2 ), and MP3 player (Π 3 ). On te oter and, tere are 5 dfferent tasks: H.263 encoder (τ 1 ), H.263 decoder (τ 2 ), MP3 decoder (τ 3 ), G.723 encoder (τ 4 ), and G.723 decoder (τ 5 ). Fgure 1(a) sows wc tasks compose wc mode of operaton. For nstance, te vdeo pone mode runs 4 tasks {τ 1,τ 2,τ 4,τ 5 } concurrently. Te task perod T j s dependent on te mode. Task τ 2 n Π 2 mode s sceduled twce as frequent as n Π 1 snce te task decodes 20 frames per second n te vdeo player mode Π 2 wle t decodes 10 frames n Π 1. In ts example, te task deadlnes are set equal to te task perods. In case of audo encoder/decoder tasks, we assume tat eac nvocaton processes a buffered packet of 25ms voce samples to reduce te context swtc overead. Eac task s specfed by an acyclc grap as sown n Fgure 1(b). Note tat tree functon modules are sared between tasks τ 1 and τ 2. In te grap, te annotated number on eac arc ndcates communcaton overead to be counted f te source module and te snk module of te arc are mapped onto dfferent processng elements. We do not sow te graps for tasks τ 4 and τ 5 assumng tat tey wll not be broken down nto multple processng elements. Mode Π 1 Π 2 Π 3 Task τ 1 τ 2 τ 4 τ 5 τ 2 τ 3 τ 3 Perod Deadlne (a) τ 1 τ 2 τ 3 tl k kj{ wk wk Œx ok pkj{ (b) P 0 (HW) : tme(cost) P 1 (100) P 2 (900) ME ME w :17(100) Dff DCT DCT w :5.6(20) Q Q w :4.6(24) VLC VLC w :6(20) 16 8 deq deq w :2(10) 4 12 IDCT IDCT w :5.8(20) 18 9 MC MC w1 :2.2(10), MC w2 :1(30) PD PD HD demq demq w :0.4(10) IMDCT IMDCT w :2(30) FB FB w :5(5) τ τ tj (c) Fgure 1. An example mult-mode embedded system: (a) Modes of te system, and task perods and deadlnes tat depend on modes (b) Tasks specfed by acyclc graps (c) Module-PE profle table Fgure 1(c) sows te canddate processng elements and ter cost and tmng nformaton. Ts table s called a module-pe profle table. Te trd and te fourt column ndcate tat tere are two canddate mcroprocessors. We obtan te tmng nformaton for processng element P 1 from runnng te real code x Œtx }sj Œx tj ptkj{ pkj{ m

3 wt te Armulator[6] assumng 500MHz ARM processor. Processng element P 2 s about twce faster, but nne tmes more expensve. Te second column lsts te ardware mplementatons tat wll be regarded as separate processng elements. For eac ardware mplementaton, te worst-case executon tme and te ardware cost are gven. For nstance, MC w1 as te value of 2.2 (msec) for te worst-case executon tme and 10 for te cost. We admt tat te numbers are not from te exact measurements. Packet decodng blocks PD1 and PD2, and Huffman decodng block HD ave no ardware mplementaton. 3. Proposed Cosyntess Framework Te cosyntess problem nvolves tree subproblems: selecton of approprate processng elements, mappng and scedulng of functon modules to te selected processng elements, and scedule analyss. Te proposed cosyntess framework defnes an teraton loop of tree steps tat attack te subproblems separately as depcted n Fgure 2. Te nputs to te cosyntess framework are a lbrary of canddate processng elements and a module-pe profle table as well as nput task graps. Te teraton starts wt te module-pe allocaton controller. Te module-pe allocaton controller selects a set of processng elements {p n } from te nput canddate processng elements {p m } and constructs a reduced module-pe profle table tat ncludes te selected processng elements only. Ts step s most crtcal snce desgn objectves are consdered wen selectng te approprate processng elements. If te desgn objectve s to mnmze te cost, we frst select te ceapest processor frst. Te detaled mecansm wll be explaned n te next secton. Te role of te next step s to scedule te acyclc grap of eac task to te selected processng elements n order to mnmze te scedule lengt. Wle te task graps are gven as nputs, te reduced module-pe profle table s obtaned from te PE Allocaton Controller step. Snce ts s a typcal problem of eterogeneous multprocessor (HMP) scedulng, we use any eterogeneous sceduler n ts step. We obtan te scedule result and te scedule lengt sl(τ j,pe) for task τ j. We apply ts step for eac task grap separately. An nterestng observaton n ts step s tat te sceduler may not consume all selected processng elements to furter reduce te system cost f possble. Te next step s te performance evaluaton step. It frst cecks weter te desgn constrants are satsfed. Based on te scedule lengts of all tasks obtaned from te prevous step, we compute te utlzaton factors for scedulablty analyss. If te scedulablty constrant s satsfed, t may end te teraton and record te scedulng results. In case tradeoffs between multple objectves are searced, t records te scedule results and restarts te teraton untl all desred number of optmal ponts are collected. If any desgn constrant s volated, t passes te scedulng results and volaton nformaton to te PE Allocaton Controller to select oter processng elements. More detaled dscusson can be found elsewere [7]. One of te key benefts of suc modular approac s extensblty. Wtout modfcaton of te core mappng and scedulng step, we can add more desgn constrants to te performance evaluaton step. More processng elements can be added to te PE Allocaton Controller seamlessly. Even multple desgn objectves can be consdered wtout modfyng te core mappng and scedulng step. Second beneft s adaptablty. We can easly cange te mappng and scedulng algortm even toug our mplementaton uses a specfc HMP sceduler, called te BIL sceduler[8], based on a lst scedulng eurstc. It s reported tat ts specfc sceduler performs reasonably good wle tme complexty s order of magntude faster tan oter well-formulated algortms. Anoter adaptaton can be found n coosng te rgt scedulablty test for a gven real-tme sceduler. Only performance evaluaton step s modfed to use te modfed scedulablty test. Task graps Heterogeneous Multprocessor Sceduler scedulng result Tme Table Performance Evaluaton Result Success PE Allocaton Controller Fal {P n } Fgure 2. Te proposed cosyntess framework Module-PE profle table {P m } canddate Processor elements 3.1 Tme Complexty Te worst case teraton counts of te proposed algortm s p were p s te total number of te canddate processng elements because t adds one processng element at a tme. For eac teraton, we call te HMP sceduler p r N t tmes were p r s te number of remanng canddate processng elements and N t s te number of tasks. To select te best processng element, we call te HMP sceduler once for eac canddate processng element even toug we can prune te searc tree drastcally n real mplementaton. If we let te tme complexty of te HMP sceduler as S, te total tme complexty becomes O(Sp 2 N t ). Te tme complexty of te HMP sceduler depends on te sze of te task graps and te number of selected processng elements. Even for a sngle mode system, te proposed tecnque as more advantageous n terms of tme complexty tan oter prevous approaces suc as genetc algortms and nteger lnear programmng. It s well-known tat te ILP approac s probtvely complex to solve even reasonable sze problems. MOGAC[4] uses a genetc algortm to solve cosyntess problem for mult-task systems. It as muc larger tme complexty tan ours due to two man reasons. Frst, te problem sze s proportonal to te number of tasks wle te tme complexty s proportonal to te number of tasks n our proposed approac. If te problem sze grows, te tme complexty of a genetc algortm grows muc faster n general. Second, to satsfy te scedulablty constrant, tey consder a yper-perod tat s te least common multple of te tasks perods. If te task perods are dfferent eac oter, te yper-perod can be uge and te problem sze can be uge proportonally. On te oter and, te proposed algortm uses te scedulablty test wtout problem sze ncrement, assumng tat a real-tme operatng system s used.

4 4. Processng Element Selecton In ts secton, we explan ow te PE allocaton controller selects te processng elements to aceve te desgn objectves. For smplcty, we assume tat te desgn objectve s to mnmze te system cost. And we use a smple example to sow ow te algortm proceeds. Consder an example of Fgure 3 tat as two modes of operaton and two dfferent tasks. Mode Π 1 needs two tasks wle mode Π 2 needs te second task only. Two tasks consst of tree functon modules respectvely, wle two functon modules are sared between two tasks. We assume tat te perod of task 1 and task 2 n mode Π 1 s 40 and 60 respectvely, and task 2 n mode Π Tere are two canddate processors and 6 dfferent ardware mplementatons for te consttuent functon modules as sown n te module-pe profle table of Fgure 3(b). Snce te desgn objectve s to mnmze te system cost, ntally te PE Allocaton Controller allocates te ceapest processng element: P 1 n ts example. Te reduced module-pe profle table can be depcted as Fgure 3(c) were nfnte tme ndcates te correspondng processng element s not selected. Consequently te HMP sceduler maps all modules onto te PE's of mnmum cost P 1 as dsplayed n Fgure 3(d). We obtan two separate scedulng results for two task graps. Π 1 Π 2 task 1 task 2 task 2 Perod Deadlne Z j ˆš (a) P 0 (HW):tme(cost) P 1 (10) P 2 (60) A A w :1(12) 7 2 B B w1 :2(5),B w2 :1(15) 8 3 C C w1 :2(10),C w2 :1(20) 10 5 D D w :4(10) 16 5 (b) w ^ \ ˆš j \ \ k ˆš P 0 P 1 P 2 A 7 B 8 C 10 D 16 (c) ^ \ ˆš (d) Fgure 3. (a) Modes and task graps (b) Module-PE profle table (c) Intally reduced module-pe profle table (d) Scedulng results Te next step s te performance evaluaton step tat tests f tasks are scedulable. As dscussed earler, t s utlzaton tat s a measure to determne te scedulablty for a gven real-tme sceduler suc as rate-monotonc, earlest deadlne frst and so on. If te utlzaton becomes larger tan te gven utlzaton constrant ten te evaluaton fals and more PE's need to be allocated. From te scedulng result n Fgure 3(d), utlzaton U Π 1 of mode Π 1 becomes 1.14 ( = + ) and U Π becomes k Z ( = ). If we assume tat te utlzaton constrant s 1.0, 30 we sould allocate more PE's n order to reduce te scedulng lengt of all tasks untl utlzaton constrant s satsfed for all tasks. Now, we arrve at te core of te selecton tecnque. Among many canddate processng elements, we want to select anoter PE, wc reduces te task executon tmes as muc as possble, but mnmzes te cost ncrement. We defne te expected utlzaton decrement() and te expected cost ncrement() for eac canddate processng element. Furtermore, we defne te slack as te dfference between te utlzaton constrant U * and te current utlzaton n order to avod reducng te utlzaton factor too muc wt more expensve PE. * Slack Π = U ( PE) U Π (2). Wle (p n ) s smply te cost of processng element p n, (p n ) s defned as te dfference between te utlzaton before allocatng p n and te utlzaton after allocatng p n. ( pn ) = mn( U Π ( PE) U Π ( PE { p Slack n}), Π ) (3). Π Π scedule lengt task 1 task 2 A w B w B w C w C w D w P (a) P 0 P 1 P 2 A 1 7 B 8 C 10 D 16 w W w w W w ˆš ˆš (b) (c) Fgure 4. (a) value for all canddate processng elements (b) Modfed module-pe profle table after A w s selected (c) Scedulng results After computng s and s of all PE's, we coose an entry tat as te largest value among unselected PE's snce te utlzaton s expected to decrease sgnfcantly wt mnmal cost ncrease. And we modfy te reduced module-pe profle table and pass t to te HMP sceduler. It s not guaranteed owever tat j k ^

5 te modules are mapped to te newly selected PE. Modules wll be sceduled onto te PE only wen te total scedule lengt s actually reduced consderng communcaton overeads. Fgure 4(a) represents and values of canddate processng elements at te onset of te second teraton. For example, (A w ) s te sum of mn( 1.14 ( + ),0.14) of mode Π 1 and mn( 1.03,0.03) of mode Π 2. In ts example, 30 A w s cosen snce ts rato s te largest. Te HMP scedulng result s sown n Fgure 4(c). Snce we can scedule all tasks wtn te utlzaton constrant, we ext from te teraton loop. Te mult-functon problem[9] s a cosyntess problem to support multple functons or applcatons of wc only one s executed at any nstant. Snce te problem allows eac mode or applcaton to ave one task, t s a sub-problem of te cosyntess problem dscussed n ts paper. Te fact tat eac mode as one task enables us not to compute utlzaton. Instead of utlzaton, te scedule lengt of eac task can be used to compute expected utlzaton ncrement. Te oter procedures remans as descrbed n te prevous secton. 5. Expermental Results We apply te proposed tecnque to te mult-mode embedded system descrbed n secton 2. Te HW speed and HW cost nformaton s reasonably estmated wle not obtaned from real mplementaton. For comparson, we frst apply te proposed cosyntess algortm for eac mode of operaton separately and add up te estmated system cost at te end. Table 1 sows wc processng elements are selected and wat s te resultant system cost. Wle processor P 1 s commonly selected, dfferent ardware mplementatons are selected for vdeo pone and vdeo player applcatons. As a result, 5 processng elements are selected and te system cost becomes 235. Table 1. Results wtout consderng mult-mode mult-task Mode Used PE s Cost vdeo pone ME w, IDCT w, P vdeo player MC w1, FB w, P MP3 player P Total ME w, IDCT w, P 1, MC w1, FB w 235 Now, we apply te proposed algortm to all modes togeter consderng te resource sarng possblty. As sown n Table 2, te vdeo player mode selects a dfferent set of ardware mplementatons. Instead of selectng Moton Compensaton and Flter Bank blocks, t selects IDCT block for HW mplementaton snce te IDCT HW s already selected n te vdeo-pone mode. Snce resource sarng s successfully exploted n te proposed tecnque, te total system cost s reduced to 220. Te proposed algortm as been mplemented n C++ on a codesgn framework[10]. It takes 0.1 seconds wt Pentum 667 MHz processors. Consderng te problem sze of 3 modes, 5 tasks, 16 functon modules, and 13 processng elements, te tme complexty s reasonable. Table 2. Results wt consderng mult-mode mult-task Mode Used PE s Cost vdeo pone ME w, IDCT w, P vdeo player IDCT w, P MP3 player P Total ME w, IDCT w, P We apply te proposed tecnque to te examples used n Hou's researc[3]. Tey ave tree processng elements and four tasks wc ncludes 10 modules. Tey tested tree examples of task combnaton, wc we nterpret tem as tree dfferent modes of operaton: Π 1, Π 2 and Π 3 as sown Table 3. If we use te same task perods as [3], we cannot reduce system cost furter snce ndependent applcaton of te cosyntess algortm to eac mode also selects two processng elements. However f we prolong te perod of τ 1 and τ 3 n Π 2 to 2000, ten te system cost ncreases snce te algortm allocates lower cost PE for tasks n Π 2 nstead of reusng PE's allocated for tasks n te oter modes. Table 3. Hou's task graps : perod and system cost Π 1 Π 2 Π 3 task 1 task 2 task 1 task 3 task 3 task 4 orgnal perod relaxed perod cost wtout consderng mult-mode cost wt consderng mult-mode orgnal perod relaxed perod Conclusons In ts paper, a HW/SW cosyntess framework s proposed for mult-mode mult-task embedded systems wt real-tme constrants. Te proposed teratve consyntess procedure conssts of tree steps: selecton of processng elements ncludng ASIC core mplementatons, mappng and scedulng of task graps onto te selected processng elements, and scedulablty test. Unlke te prevous approaces, we take nto account of task sarng between operaton modes as well as HW resource sarng between tasks. As a result, te proposed algortm aceves about 10% reducton of system cost wt an example mult-mode embedded system, compared wt an approac wtout consderng te resource sarng opportuntes. Snce te tme complexty of te proposed algortm s only lnear to te number of tasks, t s applcable for large sze applcatons. Te key benefts of te proposed framework are extensblty and adaptablty. Even toug we concern about te scedulablty and te system cost only n ts paper, more desgn constrants and desgn objectves can be easly augmented. Te man dffculty of usng ts approac to practcal system desgn s constructng te module-pe profle table, wc s assumed to be gven n ts paper.

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