A Heuristic Method for Statistical Digital Circuit Sizing

Transcription

1 A Heurstc Method for Statstcal Dgtal Crcut Szng Stephen Boyd a, Seung-Jean Km a, Dnesh Patl b, Mark Horowtz b a Informaton Systems Laboratory, Department of Electrcal Engneerng, Stanford Unversty, CA, USA 94305; b Computer Systems Laboratory, Department of Electrcal Engneerng, Stanford Unversty, CA, USA ABSTRACT In ths paper we gve a bref overvew of a heurstc method for approxmately solvng a statstcal dgtal crcut szng problem, by reducng t to a related determnstc szng problem that ncludes extra margns n each of the gate delays to account for the varaton. Snce the method s based on solvng a determnstc szng problem, t readly handles large-scale problems. Numercal experments show that the resultng desgns are often substantally better than one n whch the varaton n delay s gnored, and often qute close to the global optmum. Moreover, the desgns seem to be good despte the smplcty of the statstcal model (whch gnores gate dstrbuton shape, correlatons, and so on). We llustrate the method on a 32-bt Ladner-Fscher adder, wth a smple resstor-capactor (RC) delay model, and a Pelgrom model of delay varaton. Keywords: Desgn for manufacturng, desgn for yeld, statstcal crcut szng 1. INTRODUCTION For current ntegrated crcut (IC) technologes, statstcal uncertanty and process varaton can be ndrectly handled by ncorporatng smple margns n the tmng and other crtcal constrants, or by a post-desgn step that does centerng or yeld mprovement. 1 3 As devce dmensons shrnk, however, growng (relatve) statstcal uncertanty and process varaton wll requre an approach where desgn and yeld optmzaton are combned. 4 7 The ncreasng mportance of process varaton explans the growng nterest n process varaton modelng, and statstcal tmng analyss and desgn of of dgtal crcuts In statstcal desgn we take nto account statstcal varaton n the devce, process, and envronment parameters for each gate. In other words, we consder local varatons n the model parameters for gate delay, energy, and leakage current, wth each gate havng ts own set of parameter values, drawn from some dstrbuton. (Ths s n contrast to the framework for robust desgn over corners, where the gate model parameters varatons are global,.e., the same for all gates.) In the smplest case, the parameter values for each gate are modeled as ndependent random varables, but more sophstcated models can nclude correlaton between the parameters assocated wth dfferent gates. Another approach s to nclude two unknown terms n the parameters of each gate: one s a systematc one, global for the whole crcut (as n robust desgn over corners), and the other s the local uncertanty we consder here. Ths leads to a blend of robust desgn over corners (to handle global parameter varaton) and statstcal desgn (to handle local parameter varaton). Whle there are many possble choces of objectves n statstcal desgn, we concentrate on a typcal one, an upper quantle (e.g., 95%) of the cycle tme. Szng a crcut that meets a tmng specfcaton wth hgh probablty, despte statstcal varaton, s called statstcal crcut szng. It s closely related to desgn for yeld (DFY), desgn for manufacture (DFM), and desgn centerng. There are many exact or drect methods for solvng determnstc crcut szng problems, even for largescale problems; see Ref. 13 for those methods for dgtal crcut szng. There are far fewer methods for solvng Further author nformaton: (Send correspondence to S. Boyd.) S. Boyd: E-mal: boyd@stanford.edu, Telephone: S. Km: E-mal: sjkm@stanford.edu, Telephone: D. Patl: E-mal: ddpatl@stanford.edu, Telephone: M. Horowtz: E-mal: horowtz@stanford.edu, Telephone:

2 statstcal crcut szng problems, and these are computatonally far more demandng (or ntractable), even for small problems. Moreover, the desgns obtaned depend on detals of the gate delay dstrbutons, whch are often not well known n practcal applcatons. In ths paper we descrbe a smple heurstc method 14, 15 for approxmately solvng a statstcal dgtal crcut szng problem, by reducng t to a related determnstc szng problem that ncludes extra margns n each of the gate delays to account for the varaton. Snce the method s based on solvng a determnstc szng problem, t readly handles large-scale problems. Numercal experments show that the resultng desgns are often substantally better than one n whch the varaton n delay s gnored, and often qute close to the global optmum. 14 Moreover, the desgns seem to be good despte the smplcty of the statstcal model (whch gnores gate dstrbuton shape, correlatons, and so on) STATISTICAL DESIGN OF DIGITAL CIRCUITS We frst consder a basc determnstc gate scalng problem for a crcut consstng of n gates, each wth a varable scale factor that sets ts drve strength. The goal s to choose the scale factors to gve mnmum delay, subject to lmts on the total area and power. Ths can be expressed as the optmzaton problem mnmze D subject to P P max, A A max, 1 x, = 1,..., n, (1) where D s the maxmum crcut delay (over all paths), A s the total area, and P s the power. The desgn varables are the gate scale factors x 1,..., x n, whch scale the wdths of the devces used to form the gates. Here P max and A max are gven lmts on the total power and area. Now we consder the effects of parameter varaton. Statstcal varaton n the gate parameter values nduces statstcal varaton n the performance objectves D and P, whch are descrbed by probablty dstrbutons, that depend on the choce of scalng factors,.e., x. We can modfy the basc determnstc problem (1) by requrng that the power constrant should hold wth some mnmum probablty (or relablty) such as 95%, and takng as objectve the 95% quantle (say) of delay: mnmze Q.95 (D) subject to Q.95 (P) P max, A A max, 1 x, = 1,..., n. (2) Here D and P are random varables, and Q.95 (X) denotes the 95% quantle of the random varable X. In the basc statstcal desgn problem formulaton (2), we nsst that 95% of the crcuts meet the power constrant, and we judge a desgn by the 95% quantle of ts delay. The formulaton (2) s a stochastc optmzaton problem. The desgn varables are stll just the gate scale factors x 1,..., x n, but the objectve Q.95 (D) and constrant functon Q.95 (P) are now very complcated functons of x. The stochastc optmzaton problem (2) s very dffcult or mpossble to solve exactly, so most approaches are heurstc, and attempt to solve the problem approxmately. The statstcal analyss problem, however, s more tractable than the statstcal desgn problem (2). If we are gven a proposed desgn x, we can fnd the assocated probablty dstrbutons of the gate delays and powers (ncludng any correlatons or dependences among them), so we can estmate Q.95 (D) and Q.95 (P) va Monte Carlo analyss. Monte Carlo analyss reveals not only these quantles of the random varables, but gves estmates of ther probablty densty functons (PDFs) as well. We wll llustrate our method usng smple models for power, delay, and ther statstcal varaton, as a functon of gate scale factor and load capactance. Wth these models, the fnal optmzaton problem has a specal form: t s a (generalzed) geometrc program (GP), a specal type of optmzaton problem that can be solved globally and effcently. 16 We refer the reader to Ref. 17 for an ntroducton to geometrc programmng, some of the basc trcks used to formulate problems n GP form, a number of examples, and an extensve lst of references. An mplementaton of a prmal-dual nteror-pont method for GP s avalable n GGPLAB, a Matlab-based toolbox for GP 18 and n the MOSEK software package. 19 GP-based crcut szng s by no means new; t has been used for dgtal crcuts snce the 1980s, 13, 20 as well as analog crcuts 21, 22 and RF crcuts

3 2.1. Statstcal power constrant The statstcal power constrant Q.95 (P) P max s not very dffcult to handle, at least approxmately, snce the power s the sum of the ndvdual gate powers P. Assumng the parameter varatons are ndependent (enough) and the crcut contans a large number of gates (whch holds n problems of nterest) the power P has a standard devaton that s small relatve to ts mean EP. Thus, we can use EP P max as a reasonable approxmaton of Q.95 (P) P max. Snce P = n =1 P, our approxmaton of the statstcal power constrant Q.95 (P) P max reduces to n EP P max. =1 Thus, we can take nto account the effect of statstcal varaton on total crcut power by replacng the nomnal gate power model wth a mean gate power model (where the mean s over the parameter varaton). The mean gate power can be well approxmated n a form compatble wth geometrc programmng. 13 Ths smple treatment of the power constrant reles on the fact that n a sum of a large number of random varables, whch are uncorrelated (or just not too correlated), the random varatons tend to cancel each other out, leadng to (relatvely) lower varaton n the sum Statstcal delay analyss The effect of statstcal varaton n the gate delays s far more dffcult to analyze than the effect of varaton n the gate powers, and s what makes the statstcal gate szng problem (2) challengng. Assumng that the varatons n gate delays are ndependent, the delay of the paths, whch are sums of gate delays, have reduced varance, by a factor on the order of the number of gates on the path (wth s typcally not large, on the order of 10). Thus, the paths stll exhbt substantal statstcal varaton n delay. The overall delay of a crcut s the maxmum of the path delays. The maxmum of a set of random varables behaves very dfferently from a sum. The maxmum of a set of random varables can have a dstrbuton wth a strong rght skew, and a varance substantally larger than the varance of the ndvdual varables. In a sum of random varables, the ndvdual random varatons tend to cancel each other out; for the sum to be large, t s requred that many of the ndvdual varable should be large, whch s very unlkely. But n a maxmum, no such cancellaton occurs; all that s requred for the maxmum to be large s that just one of the ndvdual varables should be large. Wth a large number of random varables, wth enough ndependence, t s qute lkely that one of them s large. We use the alpha-power law model 27 and Pelgrom s model, 28 to carry out an analyss of gate delay varaton, nduced by varaton n the threshold voltage V th, a crtcal electrcal parameter of the devces n a gate. Gate delay vares wth threshold voltage accordng to the alpha-power law model D V dd (V dd V th ) α, where α s a parameter typcally between 1.3 and 2, and V dd s the supply voltage. One smple and commonly used model for threshold voltage varaton s Pelgrom s model, whch predcts that the threshold voltage of the devces n a gate has varance σ 2 V th = σ 2 V th x 1, where σ 2 V th s the varance for a unt scaled gate. Ths model predcts that larger gates have smaller varaton n threshold voltage than smaller ones, due to spatal averagng. Assumng the statstcal varaton n V th s not too large, we have σ D σ ασ Vth V th = (V dd V th ) x 1/2 D, (3) V th where σ 2 V th s the varance for a unt scaled gate and σ s the standard devaton of the gate delay D. Thus the relatve delay varaton decreases wth ncreasng devce area. Moreover, the gate delay standard devaton s a generalzed posynomal of the scale factors, whenever D s, and so s compatble wth geometrc programmng. 13

4 The dstrbuton of the overall crcut delay s found from the gate delay dstrbutons, propagated through the functon that maps gate delays nto overall crcut delay, whch s a maxmum of a large number of sums. There s no smple analyss or descrpton of ths dstrbuton, whch, as mentoned above, can have a large rght skew. For a fxed desgn (.e., choce of x), however, we can compute a good estmate of ths dstrbuton by Monte Carlo analyss. 3. A HEURISTIC FOR STATISTICAL DESIGN In ths secton we descrbe a smple heurstc for the statstcal desgn problem (2). We start wth a (determnstc) model for each gate, whch gves the mean delay D for gate. To ths mean gate delay we add a zero-mean random varable wth varance σ 2, whch represents the statstcal fluctuaton or uncertanty n the gate delay. We assume that σ s, lke D, a functon of the scale factor, load capactance, and nput sgnal transton tmes. The rato σ /D s a measure of the relatve or percentage varaton n the gate delay. Now we can descrbe the heurstc method. We form a surrogate delay model D = D + κ σ, where κ are constants (often all the same), typcally between 1 and 3, that are used to trade off mean and varance of the overall delay. The extra term κ σ adds an extra margn n the gate delay model, that scales wth ncreasng gate delay varance. Now we optmze the crcut as usual, usng the surrogate delays D n place of the (mean) delays D. Note that when κ = 0, ths method s the same as the standard (non-statstcal) desgn method. We can analyze the resultng desgn usng Monte Carlo analyss, coupled wth statc tmng analyss. We can then adjust the constants κ for optmum performance (for example, estmated yeld). For example, desgns can be carred out wth all κ constant, and equal to the values κ = 2, κ = 2.5, κ = 3; the best of the resultng three desgns s taken as the fnal desgn. Ths smple heurstc method s smlar n sprt to the general method of regularzaton, 29 n whch an extra penalty term s added to a problem to approxmately account for some varaton n the problem data. It s 30, 31 also related to robust optmzaton, a more sophstcated and recent approach to handlng uncertanty and varaton n optmzaton problem data, n whch an explct model of data uncertanty s used, and the objectve s taken to be the average or worst-case value of the objectve, over the parameter varaton set. Ths smple heurstc method looks smple, but s more sophstcated than t appears, snce the extra margns are added on a gate-by-gate bass, and not on a path-by-path bass. The qualty of the resultng suboptmal desgns can be assessed usng wdely applcable lower bounds on achevable performance n optmal statstcal desgn. 14 In some cases, the method yelds a desgn that s provably close to the global optmum of the (dffcult) stochastc optmzaton problem STATISTICAL DESIGN EXAMPLE We llustrate the heurstc method for statstcal desgn on a 32-bt Ladner-Fsher adder, 32 consstng of 459 gates, ncludng 64 nput gates and 32 output gates, and 1714 arcs. The crcut has a total of 3214 paths from nput gates to output gates. The maxmum path length s 12. We use a smplfed statc tmng model, wth a sngle delay for each gate (gnorng dfferng rse and fall tmes, dfferent delays for dfferent gate transtons, and the effects of sgnal slopes). The scale factor x 1 scales the wdths of the devces used to form the gate and therefore affects ts drve strength, nput capactance, and area. (The same method can be appled to a full custom desgn, n whch each devce s szed ndvdually. 15 ) The scale factor x = 1 corresponds to a mnmum szed gate, and a scale factor x = 16 (say) corresponds to a verson of the gate n whch all devces have wdth 16 tmes the wdths of the devces n the mnmum szed gate. n nt Gate has three parameters: an nput capactance, an ntrnsc or nternal capactance, and drvng resstance. The nput and ntrnsc capactances are modeled as lnear functons of the scale factor, R nt C n = n x, C nt = nt x,

5 Table 1. The 5 gate types used n the Ladner-Fsher adder. The frst column gves the gate name; the second column gves the logc functon the gate mplements, and the remanng 4 columns gve the model parameters. gate type functon n nt R Ā INV A NAND2 AB NOR2 A + B AOI21 AB + C OAI21 (A + B)C n nt where and are the nput capactance and ntrnsc capactance of gate wth unt scalng. The drvng resstance R s nversely proportonal to the scale factor: R = R /x, where R s the drvng resstance of gate wth unt scale factor. Let C L drves. Then, for an output gate, C L = Cj n, j FO() be the load capactance that gate where FO() s the set of fan-out gates of. Usng the smple resstor-capactor model of a gate and ts load, we approxmate the gate delay as D (x) = 0.69R (C nt + C L ), (4) whch s the tme requred for the output voltage of an RC crcut to reach the mdpont between the logc voltage levels. Another parameter of gate s the area. We approxmate the (physcal) area of gate as proportonal to the scale factor x, so the total area of the crcut has the form A = n x Ā, =1 where Ā s the area of gate wth unt scalng. The gate area s the total wdth of the devces n the gate (snce the gate lengths are always chosen to be the smallest value allowed n the technology.) The Ladner-Fsher adder contans 5 types of gates, wth assocated functons and model parameters lsted n Table 1. The capactance unt s the capactance of the NMOS devce n a unt scaled nverter, and the area unt s the wdth of the NMOS devce n a unt scaled nverter. The drve strength value R = 0.48 s chosen so that the delay of a unt sze nverter wth no load s = 1. In other words, the tme unt s normalzed to the delay of a unt scale nverter, wth no load, denoted by τ. The model parameters come from the logcal effort model. 33 The expresson (4) gves the mean delay of a gate. We take the standard devaton of the gate delay to be σ (x) = γx 1/2 D (x), whch s motvated by Pelgrom s model as dscussed above. The parameter γ gves the relatve varaton for a mnmum szed gate (.e., x = 1). We used the model parameter γ = 0.15, whch means that for a mnmum szed gate, the delay standard devaton s 15% of ts mean, and that ths rato decreases wth ncreasng gate sze. We assume that the delay dstrbutons are Gaussan and ndependent. The actual gate delay dstrbuton cannot be exactly Gaussan, of course, snce a Gaussan varable has a postve probablty of beng negatve. But

6 Table 2. Comparson of nomnal and statstcal desgns. nomnal delay ED σ D Q.95 (D) nomnal desgn statstcal desgn statstcal desgn frequency PSfrag replacements nomnal optmal desgn D Fgure 1. Dstrbutons of crcut delay for nomnal and statstcal desgns. snce each gate delay satsfes σ/µ 0.15, the probablty of a negatve gate delay s vanshngly small. In fact, modelng the statstcs of gate delay s an area of actve research, wth many open ssues In any case, we have found that the desgns produced by our method are not senstve to detals of the gate dstrbuton shape. 14 For the optmzaton problems, we mpose a constrant on the area, as well as lower bounds on the scale factors: A 15000, 1 x, = 1,..., n. (5) The load capactance of each prmary output s taken as C L = 6. Monte Carlo analyss reveals that the heurstc statstcal desgn method gves good results wth κ = 2. The mean delay and varance model descrbed above are both posynomal functons of x, as are the constrant functons, so the surrogate crcut szng problem can be formulated as a (generalzed) geometrc program. The performance of the statstcal desgn, found by Monte Carlo analyss wth 5000 samples, s compared to the nomnal desgn (.e., the one obtaned by gnorng the statstcal varaton) n Table 2. The robust desgn has a nomnal crcut delay (.e., a crcut delay gnorng statstcal varaton) of 45.7, only 1.3% more than the nomnal desgn. When we take statstcal varaton nto account, however, the two desgns dffer. The 95% crcut delay for the nomnal optmal desgn s 50.4, whch s 11.8% more than the nomnal crcut delay. For the robust desgn, the 95% crcut delay s 48.2, whch s only 5.6% more than the nomnal optmal crcut delay. Thus, the statstcal desgn has reduced the effect of statstcal delay varaton by a factor of around 2, compared to the nomnal optmal desgn. The standard devaton of the statstcal desgn s also reduced by a factor around 2, compared to the nomnal desgn. The dstrbutons of the delay for the nomnal and statstcal desgns (estmated by Monte Carlo smulaton) are shown n Fg. 1.

7 path delay std. dev. path delay std. dev. PSfrag replacements nomnal optmal desgn mean path delay statstcal desgn mean path delay Fgure 2. Scatter plots of path delay mean versus path delay standard devaton, for the nomnal desgn (top) and statstcal desgn (bottom) Some nsght nto why the statstcal desgn performs better than the nomnal desgn can be found n Fg. 2, whch shows scatter plots of mean delay versus standard devaton for all 3214 paths n the Ladner-Fscher adder, for the nomnal and statstcal desgns. The problematc paths are the ones at the upper rght, whch represent paths that are near crtcal, and n addton have large standard devaton. The plots show that n the nomnal desgn, a number of paths wth large expected delays have large standard devaton; n the statstcal desgn, however, the varances of the paths wth large expected delays are smaller; paths wth relatvely small expected delays, however, have relatvely larger varances. 5. CONCLUSIONS We have descrbed a heurstc method for statstcal szng of a dgtal crcut, by relatng t to a related determnstc szng problem whch ncludes extra margns n each of the gate delays to account for the varaton, usng Monte Carlo analyss to verfy the performance of the desgns, and choosng the best one. Our computatonal experence 14, 15 wth the method so far suggests that the heurstc method produces desgns that are often far superor to the nomnal optmal desgn (obtaned by gnorng statstcal varaton), are often provably close to the global optmum, are not very senstve to the detals of the ndvdual gate delay dstrbutons or correlatons among them. We have extended the method descrbed here to problems wth more accurate delay models, wth dfferent delay models for rsng and fallng sgnals, dfferent nput/output pars for each gate, and effects of sgnal 15, 38 slope. In the desgn problem we sze ndvdual devces (as opposed to whole gates as n the example consdered here), and take nto account power as well as area.

8 Acknowledgments Ths materal s supported n part by the Natonal Scence Foundaton under grants # and (through October 2005) # , by the Ar Force Offce of Scentfc Research under grant #F , by MARCO Focus center for Crcut & System Solutons contract #2003-CT-888, and by MIT DARPA contract #N REFERENCES 1. H. Abdel-Malek and J. Bandler, Yeld optmzaton for arbtrary statstcal dstrbutons: Part I-Theory, IEEE Transactons on Crcuts and Systems 27, pp , Apr H. Abdel-Malek and J. Bandler, Yeld optmzaton for arbtrary statstcal dstrbutons: Part II- Implementaton, IEEE Transactons on Crcuts and Systems 27, pp , Apr M. Styblnsk and L. Opalsk, Algorthms and software tools for IC yeld optmzaton based on fundamental fabrcaton parameters, IEEE Transactons on Computer-Aded Desgn 5, pp , Jan J.-T. Kong, CAD for nanometer slcon desgn challenges and success, IEEE Transactons on Very Large Scale Integraton (VLSI) Systems 12(11), pp , J. Jess, K. Kalafala, S. Nadu, R. Otten, and C. Vsweswarah, Statstcal tmng for parametrc yeld predcton of dgtal ntegrated crcuts, n Proc. of 40th Proc. IEEE/ACM Desgn Automaton Conference, pp , (Anahem, CA), June C. Vsweswarah, Death, taxes and falng chps, n Proc. of 40th IEEE/ACM Desgn Automaton Conference, pp , (Anahem, CA), June K. Whte, W. Trybula, and R. Athay, Desgn for semconductor manufacturng-perspectve, IEEE Transactons on Components, Packagng, and Manufacturng Technology-Part C 20, pp , Jan A. Agarwal, V. Zolotov, and D. Blaauw, Statstcal tmng analyss usng bounds and selectve enumeraton, IEEE Transactons on Computer-Aded Desgn of Integrated Crcuts and Systems 22(9), pp , S. Bhardwaj, S. Vrudhula, and D. Blaauw, TAU: Tmng analyss under uncertanty, n Internatonal Conference on Computer-Aded Desgn, pp , (San Jose, CA, USA), Nov H.-F. Jyu, S. Malk, S. Devadas, and K. Keutzer, Statstcal tmng analyss of combnatonal logc crcuts, IEEE Transactons on VLSI Systems 1(2), pp , A. Bramblla and P. Maffezzon, Statstcal method for the analyss of nterconnects delay n submcrometer layouts, IEEE Transactons on Compute-Aded Desgn of Integrated Crcuts and Systems 20(8), pp , H. Hashmoto and H. Onodera, A performance optmzaton method by gate szng usng statstcal statc tmng analyss, n Proc. of ACM Internatonal Symposum on Physcal Desgn, pp , (San Dego, CA), Apr S. Boyd, S.-J. Km, D. Patl, and M. Horowtz, Dgtal crcut optmzaton va geometrc programmng, Operatons Research 53(6), pp , S.-J. Km, S. Boyd, S. Yoon, D. Patl, and M. Horowtz, A heurstc for optmzng stochastc actvty networks wth applcatons to statstcal dgtal crcut szng, To appear n Optmzaton and Engneerng. Avalable from heur san opt.html. 15. D. Patl, Y. Yun, S.-J. Km, S. Boyd, and M. Horowtz, A new method for robust desgn of dgtal crcuts, n Proccedngs of the Sxth Internatonal Symposum on Qualty Electronc Desgn (ISQED) 2005, pp , IEEE Computer Socety Press, S. Boyd and L. Vandenberghe, Convex Optmzaton, Cambrdge Unversty Press, S. Boyd, S.-J. Km, L. Vandenberghe, and A. Hassb, A tutoral on geometrc programmng, To appear n Optmzaton and Engneerng. Avalable from gp tutoral.html. 18. A. Mutapcc, K. Koh, S.-J. Km, L. Vandenberghe, and S. Boyd, GGPLAB: A Smple Matlab Toolbox for Geometrc Programmng, Avalable from boyd/ggplab/. 19. MOSEK ApS, The MOSEK Optmzaton Tools Verson 2.5. User s Manual and Reference, Avalable from

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