Functional Test coverage

Transcription

1 ASTER Technologies Tested? Functional Test coverage What does it mean when a functional test passes? Christophe Lotz Peter Collins Dominique Wiatrowski ASTER Technologies ASTER Technologies SIEMENS AG Slide 1 Electronic design and production changes resulting in: Increased functional complexity of electronic boards Staggering board density Outsourcing of board manufacturing Introduction Test coverage calculations for PCBs are a key indicator in determining product quality. Slide 2

2 Physical Accessibility Loss of physical accessibility promotes alternative complimentary test techniques: Automated Optical Inspection (AOI) Automated X-ray Inspection (AXI) Flying Probe Test (FPT) Boundary-Scan Test (BST) Fault Coverage Functional Test (FT) 100% 50% Physical access Virtual access Access Slide 3 Test Techniques The test techniques are separated in two categories: Structural test: if each component on the board is separately good, the board will be good (AOI, AXI, BST, ICT, FPT, MDA). Functional test: if the board performs the function, all components are good (FT). Slide 4

3 Manufacturing Defect Universe Typical defects Missing components Wrong value Polarity Misalignment Tombstone Opens Broken leads Insufficient solder Shorts Manufacturing flow Material (Supply chain) Placement Solder Slide 5 Test Coverage Facets: Part 1 The correlation between the defect universe and the 3 main test coverage facets are tabled: MPS [1] Material Placement Solder The high level MPS representation could be broken down to show additional sub criteria such as: Absence (DNP components) Downloaded (Flash, FPGA, up) Solder shape Solder density (voiding with lead-free soldering PPVS [2] Value Presence Polarity Solder PCOLA/SOQ [3] Correct Live Presence Alignment Orientation Short Open Quality Slide 6

4 Test Coverage Facets: Part 2 The list of faults described within the defect universe are further sub-categorized as: Defects: detected by a test, or fixed by repair Deviations: located by inspection and fixed by process tuning When functional test is considered for structural testing & design validation, we need 3 main defect classes : Design defects: detected by a DRC, or by electrical DfT or DfM Production defects: MPS, PCOLA/SOQ or PPVS model Functional defects: defects attached to a block of components Slide 7 Test Coverage Facets: Part 3 The test coverage model now becomes DMPSF Design Material Design Manufacture Function Placement Solder Function Buy Materials (Supply chain) Place components Soldering Presence Polarity Slide 8

5 Complementary Test Coverage Each test technique brings a certain ability to detect the defects defined within defect universe No single solution is capable of detecting all the defects. P P V S P P V S P P V S P P V S Good coverage = combination of tests. Slide 9 Test efficiency: Production For each category (MPS) of defects (D), we associate the corresponding coverage (C). Coverage = Σ D M C M + Σ D P C P + Σ D S C S Σ D M + Σ D P + Σ D S The PPVS model is based on a coverage balanced by the defects opportunities. D f C f We need a better coverage where there are more defect opportunities! Slide 10

6 The Production test weighted coverage formulae can be expanded to cover Maintenance test. Lambda (λ) value is linked to failure in time instead of DPMO in production calculations. Coverage = Test efficiency: Maintenance λ F C F λ F Where F relates to component function i.e. value drift, dynamic characteristic drift etc; failures detected by functional test. Where B relates to component border i.e. broken joints & bonding, defective IO buffer etc; failures detected by structural test. + + λ B C λ B B Slide 11 Functional Test Functional testers are usually a challenge because: Difficult to predict test coverage unless fault simulation is undertaken. Measurement statements from the test report are too complex to link with defects. Fault diagnosis is limited or non-existent, majority of tests PASS/FAIL TestWay proposes 3 methods to create the Functional Test Coverage Report: Declaration: using schematic and/or layout viewers as input devices. Deduction: from formal test description based on customer s rules. Inheritance: test reuse in a hierarchical design flow where a functional block is associated with test coverage calculations. Slide 12

7 Declaration Method Schematic and layout viewers used to simplify coverage declaration. Slide 13 Declaration Method PPVS fault coverage can be made for each selected component, or by pin and color coded to represent coverage. PPVS coverage for device A2 indicates the following declaration: Presence 100% Polarity 100% Value 0% Solder 60% P S P V Component icon: Each square gets a color depending on the PPVS coverage. Pin icon: covered. Slide 14

8 Declaration method Declaration method can be further expanded to provide coverage predictions for specific functional test steps. Declaration by test step allows: Cross analysis to confirm that test steps are actually implemented. If a test step passes, it identifies a functional area free of defects. If test step subsequently fails that includes a previously tested functional component, the Sherlock algorithm can identify the most probable source. Slide 15 Deduction method Test Pattern Coverage Coverage is deduced from test sequences. Slide 16

9 Deduction method Deduction method makes a prediction based on premise that certain components within a functional block are covered by specific test sequences. Test sequences are described using the customer s rules CPU syntax. TestWay deducts the functional coverage from the test sequences. This approach provides good results for simple boards where test sequences are applied on simple module. Inter- Face FLASH RAM Slide 17 Inheritance method Recognition of pre-analyzed modules with corresponding coverage Derivation and accumulation for the new design. Slide 18

10 Inheritance method Inheritance method can re-use test coverage predictions associated with functional blocks. In a high hierarchical design flow, the standard modules are stored in a CAD library, or can be extracted from board schematic. A module can be reused several times on different boards. Functional test coverage details can be supplied manually, from fault simulation, or by using the declaration or deduction methods. TestWay supports Test Reuse/Design Reuse in order to avoid multiple declarations. Slide 19 Inheritance method Board During board analysis, TestWay explores the library of known modules. CPU Interface When an instance of a known module is identified on the board, the corresponding module coverage is transferred to the board design. Power The module matcher checks known module connectivity with board connectivity for 100% match. Slide 20

11 Inheritance method The following information is used to recognise/match a module/function: 1. Component reference designator 2. Component type or function 3. Pin number 4. Net name [1] and [2] are linked with the component. [3] and [4] are linked with connectivity. Slide 21 Inheritance method The module matcher manages variations in design instances that have identical functionality, such as: R1 mounted reverse (swapping between pins 1 & 2) Resistors (R1, R2 & R3) could be packed in resistor array i.e. component type and pin number become irrelevant. Connector pins (P1-A1 or P1-A2) are handled differently under certain conditions: a) Mandatory to use a certain pin. b) Function remains the same if pin is connected to different connector point. Some module components are optional e.g. DNP may be missing but function is still the same. Slide 22

12 Combining Test Strategies Functional In-Circuit Boundary-Scan TestWay simulates mixed test line: Estimate global test coverage. Minimize test technique drawbacks such as: number of test points, test time, false alarms, diagnostic inaccuracy Functional test coverage (FT) estimations can be used in conjunction with complementary test strategies to provide total fault coverage i.e. AOI, AXI, ICT, FPT and BST. Slide 23 Conclusions Technological developments introduce new problems that call for new tools, such as test coverage estimation. Throughout the product life cycle, coverage estimation permits the test process to be optimised. The optimum deployment of testers, with controlled redundancy will result in reduced costs and improved quality. In order to achieve realistic hierarchical DfT analysis of board designs, test coverage analysis must be integral to the standard design & test flow. Slide 24