Estimation of Ready Queue Processing Time Under SL Scheduling Scheme in Multiprocessors Environment

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1 D Shua, Ajali Jai & Amita Chowdhary Estimatio of Ready Queue rocessig Time Uder SL Schedulig Scheme i Multiprocessors Eviromet D Shula diwaarshula@rediffmailcom Deptt of Mathematics ad Statistics Dr HSGour Cetral Uiversity Sagar (M),470003, INDIA Ajali Jai Deptt of Computer Sciece ad Applicatios Dr HSGour Cetral Uiversity Sagar (M), , INDIA ajalidcsa@rediffmailcom Amita Chowdhary Deptt of hysics ad Electroics Dr HSGour Cetral Uiversity Sagar (M), , INDIA amita4@gmailcom Abstract CU Schedulig is a ope area of research where computer scietists used to desig efficiet schedulig algorithms for CU processes i order to get output i the efficiet maer There are may CU schedulig schemes available i literature Lottery schedulig is oe of them which adopts radom choice of processes by the processors This paper presets a ew CU schedulig scheme i the form of SL Schedulig which is foud useful ad effective By virtue of this, a attempt has bee made to estimate the total processig time of all the processes preset i ready queue waitig for their processig A umerical study is icorporated i the cotet to support the mathematical fidigs related to the estimatio of processig time Keywords: CU, Ready Queue, Schedulig, SL Schedulig (SLS), Lottery Schedulig INTRODUCTION The schedulig is a methodology of queue of processes to miimize delay ad to optimize performace of the system i the multiple processor eviromet where queues of processes exist with servers A scheduler is part of a operatig system module whose primary objective is to optimize system performace accordig to the criteria set by the system desigers It refers to a set of policies ad mechaism, built ito the operatig system, which govers the order i which wor to be doe by computer system [see Silberschatz ad Galvi [3], Stallig [9] ad Taebaum ad Woodhull [5] ] There are may CU schedulig schemes available lie FIFO, Roud Robi, LIFO, DRRA etc The lottery schedulig is oe more, based o a probabilistic schedulig algorithm for i which processes are assiged some umbers i the form of lottery ticets, ad the scheduler draws a radom ticet to select the process The distributio of ticets eed ot be uiform; gratig a process more ticets to provide a relatively higher chace of selectio This techique ca be used to approximate other schedulig algorithms, such as Iteratioal Joural of Computer Sciece ad Security, volume 4: Issue 74

2 D Shua, Ajali Jai & Amita Chowdhary shortest- job ext ad fair- share schedulig etc I other words, lottery schedulig is highly resposive because it solves the problem of starvatio also, givig each process at least oe lottery ticet which guaratees that it has o- zero probability of beig selected at each schedulig operatio Suppose that there are may processors ad each fetches a process at a time from the ready queue uder lottery schedulig scheme The this may be treated as a radom sample from the log ready queue of processes There are techiques available i the literature samplig theory by which oe ca improve upo the quality of sample This paper presets a ew schedulig scheme as SL schedulig (modified form of lottery schedulig) ad the approach has bee adopted to estimate total processig time liely to cosume if etire ready queue becomes empty A REVIEW Lottery Schedulig by Waldsparger et al [3] has recetly itroduced proportioal share scheduler that eables flexible cotrol over the relative rates at which CU- boud wor loads cosume processor time David et al [5] exteded lottery schedulig, a proportioal share resource maagemet algorithm, to provide the performace assuraces preset i traditioal o-real time process schedulers They used dyamic ticets adjustmets to icorporate ito a lottery scheduler the specializatio preset i the Free BSD scheduler to improve iteractive respose time ad reduce erel loc cotetio, which eables flexible cotrol over relative process executio rates with a ticet abstractio ad provides load isulatio amog group of processes usig cocurrecies Shula ad Jai [7, 8] examied the multilevel queue schedulig scheme ad examied the deadloc property usig stochastic process Shula ad Jai [9] preseted deficit roud robi alterated (DRRA) schedulig algorithm uder Marov chai model ad examied variety of schedulig scheme ad their relative mutual comparisos by simulatio study Raz et al [6] described jobs to service, p class of priority, ad m servers for the queue which holds tass to execute ad itroduce some simulatio results for the formula for dyamic priority calculatio for CMQ The goal is to assure that eve i worst case situatios starvatio does ot occur Cochra [4] cotais a itroductio to the methods of samplig theory with applicatios over multiple data Oe more cotributio is due to Taebaum ad Woodhull [5] 3 MOTIVATION Derivig a idea from all these cotributios, this paper is a attempt to estimate possible time duratio i case whe a ba server or power supply is suddely shut dow to avoid disaster for few miutes If some processes are ruig o differet machies the it is ot wise to stop them all of a sudde I such a case oe may desire ow after what time they all will be fiished from ready queue, the after estimatig time duratio we will be able to stop processig Therefore, it is a ope problem for researcher to estimate the total time of all processes i the ready queue liely to be cosumed before closig the systems Efficiet samplig methodologies could be useful at this level to develop computatioal techique 4 SL SCHEDULING SCHEME SL Schedulig (SLS) scheme employs a techique i which the complete ad up-to-date list of the processes is available i the Ready Queue of the system It selects oly the first process i radom maer ad the rest beig automatically selected accordig to some predetermied patter The radom umber i is radom start whose value is determied by CU logic uit The CU the estimates duratio of possible processig time of all N processes at the ed of a sessio The SL schedulig is laid dow as uder: Iteratioal Joural of Computer Sciece ad Security, volume 4: Issue 75

3 D Shua, Ajali Jai & Amita Chowdhary a) Assume N processes i the ready queue ad the umber N is such that N= holds for ay positive umber ad The system has processors i multiprocessor eviromet Every process i ready is assiged a toe of serial umber to N while arrival b) The CU restricts a sessio i which all N ready queue processes are available for executio c) Schedulig chooses radomly a serial umber i ( i )This process is assiged to the first processor Q d) The other processors Q Q are assiged processes havig serial umber [i+, i+, i+3 i + (-) ] e) At the ed of the first job processig sessio CU computes mea time of all jobs processed i a sessio Ready Radom Start + +j + (-) Queues rocessors Q 3 N Radom Start Radom Start i + i i+ +j + (-) Radom Start (+j) i+j i+ (-) Q Q i Q K Exit Bloced/ Suspeded/Waitig FIGURE : rocessig of Ready Queue uder Systematic Lottery Schedulig Scheme 5 ESTIMATION OF READY QUEUE ROCESS TIME IN A SESSION Let t deote the time of processig cosumed for ij (i=,, ; j=,, ) th j process of the th i sample, t i = Mea of the th i systematic sample Iteratioal Joural of Computer Sciece ad Security, volume 4: Issue 76

4 D Shua, Ajali Jai & Amita Chowdhary = / t ij (5) j= t = Overall process mea time of N processes i ready queue = / t = / (5) ij t i i= j= i= S = Mea square of processig time for all N processes i ready queue = /( N ) ( tij t ) = /( ) ( tij t ) i= j= i= j= (53) TABLE : The possible systematic samples together with their meas Radom Start Sample Compositio (Uits i the sample) robability Mea + +j + (-) / ++j + (-) / i i i+ i+ji+ (-) / K (+j) / t t t i t Thus rows of the table gives the -systematic radom samples The probability of selectig i th group of processes as the systematic sample is / The t i is sample mea time cosumed by K processors each to process oe job i a sessio The expected value of sample mea is E ( t i ) = / t = t (54) i= So if N=, the process sample mea provides a ubiased estimate of the etire processes ready queue mea Let t sys is mea time of oe systematic sample of size uits The tsys is estimator of ready queue mea time ad t sys = i t 5 Variace of the Estimated Mea Var ( t sys ) = / ( ti t ) i= (55) Iteratioal Joural of Computer Sciece ad Security, volume 4: Issue 77

5 D Shua, Ajali Jai & Amita Chowdhary t = (( N ) / N ) S (( ) / N ) Ssys (56) Var ( ) sys where Ssys = / ( ) i= j= t ti ij (56a) Which is the mea square amog process time uits which lie withi the same systematic samples 6 NUMERICAL ILLUSTRATION TABLE : Data Set rocesses CU Time Cosidered 30 processes i the ready queue ad their CU time as show i table with =5, =6 ad N= holds 6 Uder Systematic Lottery Schedulig (SLS) Scheme rocesses 6 CU Time rocesses CU Time rocesses 6 CU Time rocesses CU Time rocesses 6 CU Time We have tae radom samples of 6 processes from give 30 processes as show i table ad fid their sample mea time as show i table 3 TABLE 3: Computatio of Sample Mea Time for SLS Sample umber for radom start =5 Sampled rocess (=6) Sampled rocessig Time Sample Mea Time i= =30, 6 = 60, = 38, 6 = 89, = 43, p 6= Iteratioal Joural of Computer Sciece ad Security, volume 4: Issue 78

6 D Shua, Ajali Jai & Amita Chowdhary i= i=3 i=4 i=5 = 0, 7 = 33, = 43, 7 = 3, = 9, 7 = =, 8 = 43, 3 = 09, 8= 67, 3 = 47, 8 = = 40, 9 = 0, 4 = 6, 9 = 58, 4 = 94, 9 = = 59, 0 = 69, 5= 74, 0 = 84, 5 = 3, 30 = 736 TABLE 4: Computatioal Values for Total rocesses Total Numbers of rocesses N 30 Mea Time t 7333 Square of Mea Time Total Sum of Squares i= t j= ij 037 Mea Square S Variace of SL Schedulig Var ( t sys ) 3848 [ ] Cofidece Iterval: The 99% cofidece iterval is t sys 96 V ( t sys ), t sys + 96 V ( t sys ) TABLE 5: Computatio of Cofidece Itervals Radom Sample Sampled rocessig Time Total Time Sampled Mea Cofidece Iterval of Time for per process Cofidece Iterval for Total Time for complete Ready Queue 30,60,38,89,43, (5957,009) (787,367) 0,33,43,3,9, (874,796) (56,3778) Iteratioal Joural of Computer Sciece ad Security, volume 4: Issue 79

7 D Shua, Ajali Jai & Amita Chowdhary 3,43,09,67,47, (594,976) (777,359) 4 40,0,6,58,95, (349,954) (047,866) 5 59,69,74,84,3, (49,034) (87,306) 7 CONCLUDING REMARKS It is observed that SL schedulig is a more scietific way of represetig algorithm tha usual lottery schedulig The uique feature it has, to provide procedure of estimatig ready queue processig time Sice sample represetatio is better by this procedure, so the queue time estimatio is also sharper I table 5, most of cofidece itervals cotai true value withi the 99% cofidece limits It seems SL schedulig helps to estimate ready queue time processig legth i advace These estimates are useful whe suddely the system eeds to shut dow due to uavoidable reasos 8 REFERENCES Aur Agarwal System-Level Modelig of a Networ-o-Chip, Iteratioal Joural of Computer Sciece ad Security (IJCSS), 3(3):54-74, 009 Agarwal, Rii ad Kaur Lahwider O flexibility aalysis of fault tolerat multistage itercoectio etwors, Iteratioal Joural of Computer Sciece ad Security (IJCSS),(4), 0 08,008 3 Carl A Waldspurger William E Weihl Lottery Schedulig a flexible proportioal-share resource maagemet, roceedigs of the st USENIX Symposium o Operatig Systems Desig ad Implemetatio (OSDI): -, Cochra, WG Samplig Techique, Wiley Easter ublicatio, New Delhi David etrou, Garth A Gibso, Joh W Milford Implemetig Lottery Schedulig: Matchig the specializatios i Traditioal Schedulers, roceedigs of the USENIX Aual Techical Coferece USA: 66-80, Raz, D, B Itzaha, H Levy Classes, riorities ad Fairess i Queuig Systems Research report, Rutgers Uiversity, Shula, D ad Jai, Saurabh A Marov chai model for multilevel queue scheduler i operatig system, roceedigs of Iteratioal Coferece o Mathematics ad Computer Sciece, ICMCS-07, pp 5-56, Shula, D ad Jai, Saurabh Deadloc state study i security based multilevel queue schedulig scheme i operatig system, roceedigs of Natioal Coferece o Networ Security ad Maagemet, NCNSM-07, pp 66-75, Shula, D ad Jai, Saurabh A Marov chai model for Deficit Roud Robi Alterated (DRRA) schedulig algorithm, roceedigs of the Iteratioal Coferece o Mathematics ad Computer Sciece, ICMCS-08: 5-6, Shula D, Tiwari Viredra, Thaur Sajay, Ad Deshmuh, A K Share Loss Aalysis of Iteret Traffic Distributio i Computer Networs Iteratioal Joural of Computer Sciece Ad Security(IJCSS), 3(5): 44-47,009 Shula D, Tiwari Viredra, Thaur Sajay, Ad Tiwari Moha A compariso of methods for iteret traffic i computer etwor, Iteratioal Joural of Advace Networig ad Applicatios, (3): 64-69, 009 Shula D, Ojha, Shweta, Ad Jai, Sourabh, Aalysis of multilevel queue with the effect of data model approach, roceedigs of the Natioal Coferece o Research ad Developmet Treds i ICT (NCRTICT 0), 45-5, 00 Iteratioal Joural of Computer Sciece ad Security, volume 4: Issue 80

8 D Shua, Ajali Jai & Amita Chowdhary 3 Silberschatz, A ad Galvi, Operatig System Cocepts, Ed5, Joh Wiley ad Sos (Asia), Ic (999) 4 Stallig, W Operatig System, Ed5, earso Educatio, Sigapore, Idia Editio, New Delhi (004) 5 Taebaum, A ad Woodhull Operatig system, Ed 8, retice Hall of Idia, New Delhi,(000) Iteratioal Joural of Computer Sciece ad Security, volume 4: Issue 8

Statistics for Economics & Business

Statistics for Economics & Business Statistics for Ecoomics & Busiess Cofidece Iterval Estimatio Learig Objectives I this chapter, you lear: To costruct ad iterpret cofidece iterval estimates for the mea ad the proportio How to determie