The egan FET Journey Continues Using egan FETs for Envelope Tracking Buck Converters Johan Strydom Efficient Power Conversion Corporation EPC - The Leader in egan FETs PELS 2014 www.epc-co.com 1
Agenda Overview of Envelope Tracking Why egan FETs for Envelope Tracking Maximizing Device Performance Experimental Results Current Limitations Summary Q & A egan is a registered trademark of Efficient Power Conversion Corporation EPC - The Leader in egan FETs PELS 2014 www.epc-co.com 2
Overview of Envelope Tracking EPC - The Leader in egan FETs PELS 2014 www.epc-co.com 3
Why Envelope Tracking? Exabytes per Month 12 10 8 6 4 2 0 Source: Cisco VNI Mobile Data Traffic Forecast 2012 2013 2014 2015 2016 2017 66% Compound annual growth rate (CAGR) Same average Reference: Nujira.com website EPC - The Leader in egan FETs PELS 2014 www.epc-co.com 4
Effect of PAPR Average Power Peak Power Fixed supply PAPR = 0dB Peak efficiency up to 65% Average efficiency only 25% Increasing PAPR Output Probability Output Power (dbm) EPC - The Leader in egan FETs PELS 2014 www.epc-co.com 5
Effect of Envelope Tracking Average efficiency ~50% (incl. ET) Only 1/3 the losses Envelope Tracking 60 ~100MHz BW ET for 4G LTE Output Probability Average Power Output Power (dbm) EPC - The Leader in egan FETs PELS 2014 www.epc-co.com 6
Hybrid ET Implementation Improvement in switching device performance buys: Improves overall ET efficiency Increases Switcher stage bandwidth Simplifies Linear stage design / Removes it entirely? Increase system BW which increases RFPA fidelity Kimball, Don, et al. "50% PAE WCDMA basestation amplifier implemented with GaN HFETs." Compound Semiconductor Integrated Circuit Symposium, 2005. CSIC'05. IEEE. IEEE, 2005. EPC - The Leader in egan FETs PELS 2014 www.epc-co.com 7
Why egan FETs for Envelope Tracking EPC - The Leader in egan FETs PELS 2014 www.epc-co.com 8
Idealized Switching V IN T CR T VF V DS I DS V V GS I ON V PL V TH α α t EPC - The Leader in egan FETs PELS 2014 www.epc-co.com 9
Hard-Switching Figure of Merit FOM HS =(Q GD +Q GS S2) R DS(on) (pc Ω) 100 10 1 EPC Gen 4 EPC Gen 2 Vendor A Vendor B Vendor C Vendor D Vendor E 6.1x 3.5x 8.5x 25 250 Drain-to-Source Voltage (V) V DS =0.5 V DSS, I DS =20 A EPC - The Leader in egan FETs PELS 2014 www.epc-co.com 10
High Frequency egan FETs EPC Part No. BV (V) Max. R DS(ON) Min. Typical Charge (pc) (mω) Peak Id (A) (V GS = 5V, (Pulsed, 25 o C, I D = 0.5 A) T pulse = 300 µs) Q G Q GD Q GS Q OSS Q RR Typical Capacitance (pf) (V DS = 20 V; V GS = 0 V) C ISS C OSS C RSS EPC8004 40 125 7.5 358 31 110 493 0 45 17 0.4 EPC8007 40 160 6 302 25 97 406 0 39 14 0.3 EPC8008 40 325 2.9 177 12 67 211 0 25 8 0.2 EPC8009 65 138 7.5 380 36 116 769 0 47 17 0.4 EPC8005 65 275 3.8 218 18 77 414 0 29 9.7 0.2 EPC8002 65 530 2 141 9.4 59 244 0 21 5.9 0.1 EPC8003 100 300 5 315 34 110 1100 0 38 18 0.2 EPC8010 100 160 7.5 354 32 109 1509 0 47 18 0.2 egan is a registered trademark of Efficient Power Conversion Corporation EPC - The Leader in egan FETs PELS 2014 www.epc-co.com 11
Hard Switching FOM EPC - The Leader in egan FETs PELS 2014 www.epc-co.com 12
dv/dt Turn-on Immunity Q GS1 >Q GD 20V 40V Q GS1 Q GD EPC8004 egan FET EPC - The Leader in egan FETs PELS 2014 www.epc-co.com 13
Maximizing Device Performance EPC - The Leader in egan FETs PELS 2014 www.epc-co.com 14
Common Source Inductance V IN T CR T VF V IN T CR T VF I ON I ON I DS V DS I DS V V DS GS V GS V PL V TH α α t EPC - The Leader in egan FETs PELS 2014 www.epc-co.com 15
Drain Packaging Evolution Gate Source Power Loss (W) 2.5 2 1.5 1 0.5 0 egan FET SO-8 LFPAK DirectFET LGA Device Loss Breakdown 82% 18% Package Die 73% 27% 47% 53% V IN =12V V OUT =1.2V I OUT =20A F S =1MHz 18% 82% SO-8 LFPAK DirectFET LGA Efficiency (%) 90 85 80 75 70 SO-8 LFPAK DirectFET LGA 65 0.5 1 1.5 2 2.5 3 3.5 Switching Frequency (MHz) EPC - The Leader in egan FETs PELS 2014 www.epc-co.com 16
Converter Parasitics C in T SR L S : Common Source Inductance L Loop : High Frequency Power Loop Inductance Power Loss(W) 5.5 5.25 5 4.75 4.5 4.25 4 3.75 3.5 3.25 3 Power Loss vs Parasitic Inductance Ls L Loop 0 0.3 0.6 0.9 1.2 1.5 1.8 2.1 2.4 2.7 3 Parasitic Inductance (nh) V IN =12 V, V OUT =1.2 V, f sw =1 MHz, I OUT = 20 A EPC - The Leader in egan FETs PELS 2014 www.epc-co.com 17
EPC8XXX Package 2050 400 600 600 225 Drain 200 X2 Sub 850 580 Gate Return Source S 400 200 x2 450 200 All dimensions in µm EPC - The Leader in egan FETs PELS 2014 www.epc-co.com 18
Low Parasitic Layout Top Layer Vias to next layer To BUS caps Switch node Supply Return Source S Drain Sub PELS 2014 Gate Current orthogonal to drain current Vias to next layer Ground Source EPC - The Leader in egan FETs Sub Return Bottom Gate Gate Top Gate Gate Drain S www.epc-co.com 19
Low Parasitic Layout First Inner Layer Optimum power loop return To gate drive Drain Sub Optimum gate loop return Gate Return Source S To gate drive Drain Sub Optimum gate loop return Gate Return Source S EPC - The Leader in egan FETs PELS 2014 www.epc-co.com 20
EPC8000 Series Improvements Reduce active area for lower power / higher frequency operation Minimize Hard Switching Figure of Merit Complete dv/dt turn-on immunity Separate gate and power loops Minimize power loop inductance Minimize gate loop inductance EPC - The Leader in egan FETs PELS 2014 www.epc-co.com 21
Experimental Results EPC - The Leader in egan FETs PELS 2014 www.epc-co.com 22
ET Prototype Board 2X, SO-8 footprint Bus caps LM5113 EPC80XX EPC80XX EPC - The Leader in egan FETs PELS 2014 www.epc-co.com 23
20 V BUS, 10 MHz, 4 A Switching EPC - The Leader in egan FETs PELS 2014 www.epc-co.com 24,
Efficien ncy 95% 93% 91% 89% 87% 85% 83% 81% 79% 77% 75% 73% 71% Near 90% @ >4:1 step down ratio 15 V IN to 3.3 V OUT, 10 MHz 0 1 2 3 4 5 6 7 Output Power (W) EPC8007 EPC - The Leader in egan FETs PELS 2014 www.epc-co.com 25 1.2 1 0.8 0.6 0.4 0.2 0 Power Los ss (W)
42 V IN at 1 A OUT No measureable overshoot dv/dt interval 75V/ns slew rate di/dt interval Rise time ~1.0 ns Total switching time ~1.2 ns 2 ns/div and 10 V/div, 1 GHz 100:1 1pF TM probe EPC - The Leader in egan FETs PELS 2014 www.epc-co.com 26,
42 V IN, 20 V OUT, 10 MHz Conduction Switching C OSS Additional losses EPC8005 EPC - The Leader in egan FETs PELS 2014 www.epc-co.com 27
Current Limitations EPC - The Leader in egan FETs PELS 2014 www.epc-co.com 28
Parasitic Losses Bootstra ap diode Reverse recovery charge V DD IC capacitance Level Shift V DD Switch-node rising edge half-bridge driver EPC - The Leader in egan FETs PELS 2014 www.epc-co.com 29
No-load Switching 10 MHz switching, no load, large dead-time 10 V/div, 100 ma/div, 10 ns/div Expected commutation based on egan FET C OSS Initially slow rising edge Actual voltage commutation slopes are different, even though currents are the same EPC - The Leader in egan FETs PELS 2014 www.epc-co.com 30
Loss Breakdown 10 MHz switching, no load, large dead-time 10 V/div, 100 ma/div, 10 ns/div Switch-node voltage Bootstrap Q RR Actual commutation based on total C OSS including IC capacitance EPC - The Leader in egan FETs PELS 2014 www.epc-co.com 31
42 V IN, 20 V OUT, 10 MHz Conduction Switching C OSS C OSS Gate Driver Switching Q RR Bootstrap diode EPC - The Leader in egan FETs PELS 2014 www.epc-co.com 32
egan FET Limited Efficiency Calculated efficiency improvement EPC - The Leader in egan FETs PELS 2014 www.epc-co.com 33
Summary New devices enable higher switching frequencies Switching 42 V, 40 W at 10 MHz at 89% possible. Driver parasitics limit performance light load losses can be cut in half, and full load losses can be reduced by 25% EPC - The Leader in egan FETs PELS 2014 www.epc-co.com 34
Thank you! Questions? EPC - The Leader in egan FETs PELS 2014 www.epc-co.com 35
The end of the road for silicon.. is the beginning of the egan FET journey! EPC - The Leader in egan FETs PELS 2014 www.epc-co.com 36 36