EE115C Spring 2013 Digital Electronic Circuits Lecture 19: Timing Analysis
Outline Timing parameters Clock nonidealities (skew and jitter) Impact of Clk skew on timing Impact of Clk jitter on timing Flip-flop- vs. Latch-based timing Clock distribution EE115C Spring 2013 2
Synchronous Timing CLK In R Combinational 1 R Logic 2 C in C out Out EE115C Spring 2013 3
Datapath and Timing Parameters In D R1 Q Combinational Logic R2 D Q CLK t CLK1 t CLK2 t c - q t c - q, cd t su, t hold t logic t logic, cd R1 and R2 can be latches or flip-flops EE115C Spring 2013 4
Latch Parameters D Q Clk Clk D PW m T H T SU Q T Clk-Q T D-Q Delays can be different for rising and falling data transitions EE115C Spring 2013 5
Flip-Flop Parameters D Q Clk Clk D PW m T H T SU Q T Clk-Q Delays can be different for rising and falling data transitions EE115C Spring 2013 6
Timing Constraints (Cycle Time & Race Margin) In D R1 Q Combinational Logic R2 D Q CLK t CLK1 t CLK2 t c - q t c - q, cd t su, t hold t logic t logic, cd Cycle time: T Clk > t c-q + t logic + t su Race margin: t hold < t c-q,cd + t logic,cd EE115C Spring 2013 7
Outline Timing parameters Clock nonidealities (skew and jitter) Impact of Clk skew on timing Impact of Clk jitter on timing Flip-flop- vs. Latch-based timing Clock distribution EE115C Spring 2013 8
Clock Nonidealities Clock skew Spatial variation in temporally equivalent clock edges Deterministic + random, t SK Clock jitter Temporal variations in consecutive edges of the clock signal Modulation + random noise Cycle-to-cycle (short-term) t JS Long term t JL Variation of the pulse width for level-sensitive clocking EE115C Spring 2013 9
Clock Skew and Jitter Clk t SK Clk t JS Both skew and jitter affect the effective cycle time Only skew affects the race margin EE115C Spring 2013 10
Clock Skew # of registers Earliest occurrence of Clk edge Nominal T sk /2 Latest occurrence of Clk edge Nominal + T sk /2 Insertion delay Clk delay T sk Max Clk skew EE115C Spring 2013 11
Sources of Skew and Jitter 4 Power Supply Devices 2 3 Interconnect 6 Capacitive Load 1 Clock Generation 5 Temperature 7 Coupling to Adjacent Lines EE115C Spring 2013 12
Positive Skew T CLK + d CLK1 1 d T CLK 3 CLK2 2 4 d + t h Launching edge arrives before the receiving edge EE115C Spring 2013 13
Negative Skew T CLK + d CLK1 1 T CLK 3 CLK2 2 d 4 Receiving edge arrives before the launching edge EE115C Spring 2013 14
Positive and Negative Skew In R1 D Q Combinational Logic R2 D Q Combinational Logic R3 D Q CLK t CLK1 t CLK2 t CLK3 delay delay (a) Positive skew In R1 D Q Combinational Logic R2 D Q Combinational Logic R3 D Q t CLK1 t CLK2 t CLK3 delay delay CLK (b) Negative skew EE115C Spring 2013 15
Outline Timing parameters Clock nonidealities (skew and jitter) Impact of Clk skew on timing Impact of Clk jitter on timing Flip-flop- vs. Latch-based timing Clock distribution EE115C Spring 2013 16
Timing Constraints (Quick Refresh) In D R1 Q Combinational Logic R2 D Q CLK t CLK1 t CLK2 t c - q t c - q, cd t su, t hold t logic t logic, cd Cycle time: T Clk > t c-q + t logic + t su Race margin: t hold < t c-q,cd + t logic,cd EE115C Spring 2013 17
Impact of Clock Skew on Timing: Cycle Time (Long Path) Clk t c-q t logic T Clk t su δ Arrival of next cycle t c-q + t logic + t su < T Clk + d T Clk > t c-q + t logic + t su - d Neg skew demands longer T Clk EE115C Spring 2013 18
Impact of Clock Skew on Timing: Race Margin (Short Path) Clk t c-q,cd t logic,cd Clk t hold δ Data must not arrive before this time t c-q,cd + t logic,cd > t hold + d t hold + d < t c-q,cd + t logic,cd Pos skew eats up t hold EE115C Spring 2013 19
Impact of Clock Skew on Timing Positive skew improves performance T Clk > t c-q + t logic + t su - d Negative skew improves race margin t hold + d < t c-q,cd + t logic,cd Worst-case skew (t skew = d ) really matters T Clk > t c-q + t logic + t su + t skew t hold + t skew < t c-q,cd + t logic,cd Implications: Longer T Clk Smaller race margin EE115C Spring 2013 20
How to Counter Clock Skew? Negative Skew REG REG. REG log Out In REG Positive Skew Clock Distribution EE115C Spring 2013 21
Outline Timing parameters Clock nonidealities (skew and jitter) Impact of Clk skew on timing Impact of Clk jitter on timing Flip-flop- vs. Latch-based timing Clock distribution EE115C Spring 2013 22
Impact of Clock Jitter T C LK CLK -t jitter t jitter In REGS CLK t c-q, t c-q, cd t su, t hold t jitter Combinational Logic t log ic t log ic, cd EE115C Spring 2013 23
Impact of Clock Jitter on Timing: Cycle Time (Late-Early Problem) t jitter Clk t c-q t logic T Clk t su Latest point of launching Earliest arrival of next cycle t c-q + t logic + t su < T Clk t jitter t jitter T Clk > t c-q + t logic + t su + 2 t jitter EE115C Spring 2013 24
Impact of Clock Skew and Jitter: Cycle Time (Late-Early Problem) t jitter + d Clk t c-q t logic T Clk t su Latest point of launching Earliest arrival of next cycle t c-q + t logic + t su < T Clk t jitter t jitter + d T Clk > t c-q + t logic + t su + t skew + 2 t jitter EE115C Spring 2013 25
Impact of Clock Skew and Jitter: Race Margin (Early-Late Problem) Earliest point of launching Clk t c-q,cd t logic,cd Clk Latest arrival of next cycle t jitter + d t hold Nominal clock edge Data must not arrive before this time t c-q,cd + t logic,cd t jitter > t hold + t jitter + d t hold + 2 t jitter + t skew < t c-q,cd + t logic,cd EE115C Spring 2013 26
Impact of Skew and Jitter on Timing Cycle time Positive skew improves performance Negative skew reduces performance Jitter reduces performance T Clk > t c-q + t logic + t su + t skew + 2 t jitter Race Margin Skew reduces race margin Jitter reduces acceptable skew t cu : clock uncertainty t hold + 2 t jitter + t skew < t c-q,cd + t logic,cd t cu : clock uncertainty EE115C Spring 2013 27
Outline Timing parameters Clock nonidealities (skew and jitter) Impact of Clk skew on timing Impact of Clk jitter on timing Flip-flop- vs. Latch-based timing Clock distribution EE115C Spring 2013 28
Flip-Flop Based Timing Logic delay Skew Flip-flop delay Flip -flop Logic T SU = 0 T Clk-Q = 1 [Horowitz96] EE115C Spring 2013 29
Latch-Based Timing Static logic Skew L1 Latch Logic L2 Latch = 1 L2 latch L1 latch Logic Can tolerate skew! Long path = 0 Short path EE115C Spring 2013 30
Perspective: Clock Distribution
Clock Distribution H-tree CLK Clock is distributed in a tree-like fashion EE115C Spring 2013 32
Clock Distribution CLOCK H-Tree Network Observe: Only Relative Skew is Important EE115C Spring 2013 33
More Realistic H-Tree [Restle98] EE115C Spring 2013 34
Clock Network with Distributed Buffering Local Area Module Module secondary clock drivers Module Module Module Module main clock driver CLOCK Reduces absolute delay, and makes Power-Down easier Sensitive to variations in Buffer Delay EE115C Spring 2013 35
Driver The Grid System Driver GCLK GCLK Driver GCLK No RC-matching Large power Driver GCLK EE115C Spring 2013 36
Example: Dec Alpha 21164 Clock Frequency: 300 MHz, 9.3 Million Transistors Total Clock Load: 3.75 nf Power in Clock Distribution Network: 20 W (out of 50 W) Uses Two Level Clock Distribution: Single 6-stage driver at center of chip Secondary buffers drive left and right side Clock grid in Metal-3 and Metal-4 Total driver size: 58 cm! EE115C Spring 2013 37
21164 Clocking (EV5), 1995 t rise = 0.35ns t cycle = 3.3ns Clock waveform final drivers pre-driver Location of clock driver on die t skew = 150ps Single-phase clocking 2 distributed driver channels Reduced RC delay/skew Improved thermal distribution 3.75 nf clock load 58 cm final driver width Local inverters for latching Conditional clocks in caches to reduce power More complex race checking Device variation EE115C Spring 2013 38
21164 Clocking (EV5), 1995 Clock Drivers EE115C Spring 2013 39
Clock Skew in Alpha Processor EE115C Spring 2013 40
EV6 (Alpha 21264) Clocking 600 MHz, 0.35mm CMOS, 1998 t cycle = 1.67ns t rise = 0.15ns Global clock waveform t skew = 50ps PLL Multiple conditional buffered clocks 2.8 nf clock load 40 cm final driver width Reduced load/skew Reduced thermal issues Multiple clocks complicate race checking EE115C Spring 2013 41
21264 Clocking EE115C Spring 2013 42
EV6 Clock Results ps 5 10 15 20 25 30 35 40 45 50 ps 300 305 310 315 320 325 330 335 340 345 GCLK Skew (at Vdd/2 Crossings) GCLK Rise Times (20% to 80% Extrapolated to 0% to 100%) EE115C Spring 2013 43
EV7 Clock Hierarchy, 2002 152 million transistors, 15/137 logic/memory Active Skew Management and Multiple Clock Domains DLL NCLK (Mem Ctrl) DLL DLL + widely dispersed drivers + DLLs compensate static and low-frequency variation + divides design and verification effort L2L_CLK (L2 Cache) GCLK (CPU Core) PLL L2R_CLK (L2 Cache) - DLL design and verification is added work SYSCLK + tailored clocks EE115C Spring 2013 44
Alpha Processors Case Study EV4 (21064) 0.75mm, 200 MHz ~ 1992 Single global clock driver, 5 levels of buffering 35 cm driver, 3.25 nf, 40% power EV5 (21164) 0.5mm, 300 MHz ~ 1995 One central, two side clock drivers 58 cm driver, 3.75 nf, 40% power EV6 (21264) 0.35mm, 600 MHz ~ 1998 Clock grid, 4 window panes, hierarchical, gated clock domains 40 cm driver, 2.8 nf EV7 0.18mm, 1.2 GHz ~ 2002 Multiple clock domains, DLLs EE115C Spring 2013 45