Statstcal Delay Computaton Consderng Spatal Correlatons Aseem Agarwal, Davd Blaauw, *Vladmr Zolotov, *Savthr Sundareswaran, *Mn Zhao, *Kaushk Gala, *Rajendran Panda Unversty of Mchgan, Ann Arbor, MI *Motorola, Inc., Austn, TX Abstract - Process varaton has become a sgnfcant concern for statc tmng analyss. In ths paper, we present a new method for path-based statstcal tmng analyss. We frst propose a method for modelng nter- and ntra-de devce length varatons. Based on ths model, we then present an effcent method for computng the total path delay probablty dstrbuton usng a combnaton of devce length enumeraton for nter-de varaton and an analytcal for ntra-de varaton. We also propose a smple and effectve model of spatal correlaton of ntra-de devce length varaton. The analyss s then extended to nclude spatal correlaton. We test the proposed methods on paths from an ndustral hgh-performance mcroprocessor and present comparsons wth tradtonal path analyss whch does not dstngush between nter- and ntrade varatons. The characterstcs of the devce length dstrbutons were obtaned from measured data of 8 test ch wth a total of 17688 devce length measurements. Spatal correlaton data was also obtaned from these measurements. We demonstrate the accuracy of the proposed by comparng our results wth Monte-Carlo smulaton. 1INTRODUCTION Statc tmng analyss has become the prmary method for performance verfcaton of hgh performance desgns. Statc tmng analyss has the advantage that t does not requre nput vectors and has a run tme that s lnear wth the sze of the crcut. A number of methods have been proposed to ncrease the accuracy of statc tmng analyss through mproved delay models and analyss technques. In recent technologes, the varablty of crcut delay due to process varatons has become a sgnfcant concern. As process geometres contnue to shrnk, the ablty to control crtcal devce parameters s becomng ncreasngly dffcult, and sgnfcant varatons n devce length, dopng concentratons, and oxde thcknesses have resulted. These process varatons pose a sgnfcant problem for tmng yeld predcton and requre that statc tmng analyss models the crcut delay not as a determnstc value, but as a random varable. Process varatons can be classfed as systematc or random where systematc varaton are determnstc n nature and are caused by the structure of a partcular gate and ts topologcal envronment.for nstance, wre thcknesses wll polsh dfferently durng CPM dependng on the densty of the surroundng routng. Also, poly gate wdth has a determnstc dependence on the spacng of neghborng poly lnes due to lmtatons of the lthography and the applcaton of OPC methods. Random varatons are unpredctable n nature and nclude random varatons n the devce length, dscreet dopng fluctuatons, and oxde thckness varatons. Analyss of the mpact of determnstc varatons on crcut delay s relatvely straghtforward, gven accurate models of ther dependence on physcal topologes and the needed layout nformaton at the tme of analyss. Methods have been proposed to nclude determnstc devce length varatons [1] and nterconnect varatons [2] n the analyss of crcut performance. However, often the necessary models and layout nformaton for ncorporatng determnstc varatons n delay computaton are not avalable and hence, determnstc varatons are treated as random varatons. Process varatons can be further classfed as nter-de varaton and ntra-de varatons. Intra-de varatons are varatons n devce features that are present wthn a sngle chp, meanng that a devce feature vares between dfferent locatons on the same de. Often, ntra-chp varatons exhbt spatal correlatons, where devces that are close to each other have a hgher probablty of beng alke than devces that are placed far apart. Intra-de varaton also exhbt structural correlatons, meanng that devces that are structurally smlar have an ncreased lkelhood of havng smlar devce features, for nstance, devces orented n the same drecton tend to be more alke. Inter-chp varaton are varatons that occur from one de to the next, meanng that the same devce on a chp has dfferent features among dfferent de of one wafer, from wafer to wafer, and from wafer lot to wafer lot. Wth ncreased process scalng, ntrachp varatons are becomng a more domnant porton of the overall varablty of devce features, meanng that devces on the same de can no longer be treated as dentcal copes of the same devce. In ths paper, we are concerned wth the mpact of random nterand ntra-de varatons on crcut performance. Tradtonally, these process varatons have been modeled usng case analyss, where a set of worst-case and best-case devce features are constructed based on the 3-sgma ponts of ther dstrbutons. Determnstc tmng analyss s then performed for each case of devce features. A sgnfcant draw back of case based tmng analyss s that nter- and ntrade varatons cannot be dstngushed snce each devce has dentcal (best-case or worst-case) features durng the analyss. In practce, devce features vary among the devces on a chp and the lkelhood that all devces have a worst-case feature s extremely small. Case analyss s therefore pessmstc snce on an actual de, devces wth worse delay are compensated for by other devces on the same de that have better delay. The mpact of ntra-de varatons on path delay wll vary from path to path, due to dfferng number of gates n a path and ther spatal locatons. Case based tmng analyss may therefore dentfy ncorrect crtcal paths, thereby resultng n ncorrect crcut optmzaton. Wth contnued process scalng, ntra-de varatons are becomng a domnant porton of the overall process varaton and tradtonal tmng analyss wll, therefore, become too restrctve for aggressve crcut desgn. Wth ncreasng awareness of process varaton, a number of technques have been developed whch model random delay varatons and perform statstcal tmng analyss. These can be classfed nto full-chp analyss and path-based analyss es. Full-chp analyss models the delay of a crcut as a random varable and endeavors to compute ts probablty dstrbuton [3-7]. Ths task s complcated by the reconvergence between crcut paths, gvng rse to correlatons of path delays. Snce the underlyng problem has an exponental complexty, the proposed methods are heurstc n nature page 1
and have a very hgh worst-case computatonal complexty. Also, they are based on very smple delay models, where the dependence of gate delay due to slope varaton at the nput of the gate and load varaton at the output of the gate s not modeled. From both a run tme and accuracy perspectve, full chp statstcal tmng analyss s therefore not yet practcal for ndustral desgns. In a path based, determnstc tmng analyss s frst performed and the top n crtcal paths are enumerated, where n s a suffcently large number to ensure that all paths that have a sgnfcant probablty of beng crtcal on a manufactured de are ncluded. For nstance, f the delay varablty s expected to be 1% of nomnal, all paths that have a determnstc delay wthn 1% of the worst-case crcut delay must be ncluded. The delay of each path s then statstcally analyzed resultng n the probablty dstrbuton of each path delay. The 3-sgma delay (or any other desred confdence pont) s then computed for each path and s compared aganst the requred crcut performance. Ths avods the ssue of path reconvergence thereby smplfyng the problem and allowng for the use of more accurate models. Path-based statstcal tmng analyss provdes statstcal nformaton on a path-by-path bass. It accounts for ntra-de process varatons and hence elmnates the pessmsm n determnstc tmng analyss based on case fles. It also provdes a more accurate measure of whch paths are crtcal under process varablty, allowng more correct optmzaton of the crcut. In [8], a path based statstcal tmng analyss was proposed. However, ths does not nclude the load dependence of the gate delay due to varablty of fanout gates and does not address spatal correlatons of ntra-de varablty. In ths paper, we therefore propose a new path-based to statstcal tmng analyss. We accurately model varatons of gate delay due to varatons of the nput slope and output loads resultng from varatons of fann and fanout stages n the path. We propose a model where nter- and ntra-de varatons are modeled as two separate components and propose effcently methods to compute path delay varablty due to ether source and as well as ther combne ther effect. We also propose a new model for ntra-de correlatons that models the mpact of spatal separaton of gates n a crcut path. We demonstrate how the proposed analyss can be extended to effcently nclude ths spatal correlaton model. The proposed model and analyss method was appled to devce length varatons n ths paper, although extensons to other devce parameters s straghtforward. To obtan ntra-de devce length varatons and ther spatal correlaton, we examned an extensve set of devce length measurements from an ndustral.18um process. To compute the ntra-de path delay component of process varablty, we frst compute the senstvty of gate delay, output slope, and nput load wth respect to the nput slope, output load and devce length. Usng these senstvtes we then express the path delay varaton as an analytcal expresson of the devce length varaton, allowng for very effcent analyss of ntra-de varablty, ncludng an accurate model for spatal correlaton. Snce the nter-de component of path delay varablty s dependent on a sngle random varable, we can compute t effcently though enumeraton of ts probablty dstrbuton. We then compute the jont path delay dstrbuton through convoluton of nter- and ntra-de delay dstrbuton components to obtan the dstrbuton of the total delay varablty. The proposed model assumptons are valdated through monte carlo smulaton and show that the proposed yelds very accurate results. The most computatonal ntensve part of the analyss s the ntal computaton of senstvtes. Snce these senstvtes are precomputed once and do not need to be re-computed durng the analyss of ndvdual paths, the proposed s very effcent. We present results on crtcal paths from an ndustral hgh performance mcroprocessor and show that the proposed statstcal analyss can sgnfcantly mprove the accuracy of performance analyss. Furthermore, we demonstrate the mportance of ncludng spatal correlaton nformaton n the analyss, showng that gnorng such correlatons may result n an under estmaton of the computed varablty. The remander of ths paper s organzed as follows. Secton 2 dscusses the delay model assumptons and propertes. Secton 3 presents the proposed for computng the path delay dstrbuton under nter- and ntra-de devce length varablty. Secton 4 presents our model and analyss method for spatal correlaton of ntra-de varatons. Secton 5 contans expermental results and n Secton 6 we draw our conclusons. 2 STATISTICAL TIMING ANALYSIS MODEL We frst consder process varaton due to nter- and ntra-de varaton, whle gnorng spatal correlatons. Extensons of the model to nclude spatal correlaton are presented n Secton 4. We propose the followng model, where the devce length L total, of devce s the algebrac sum of a nter-de devce length L nter and ntra-de devce length varaton, L ntra, : L total, = L nter + L ntra,, (EQ 1) where L nter and L ntra, are random varables wth normal dstrbutons. All devces on a de share one varable L nter for the nter-de component of ther total devce length, whch represents the mean of the gate of a partcular de. For the ntra-de component of devce length, each devce has an separate ndependent random varable L ntra,, where all random varables L ntra, have dentcal probablty dstrbutons. Both the total varaton L total and the nter-de varaton L nter have a mean whch s equal to the nomnal value of the devce length. The ntra-de varatons L ntra, have a mean of zero. We assume that all three random varables L total, L nter, and L ntra have a normal dstrbuton, whch s a common assumpton snce devce length s a physcal quantty. It s mportant to notce, however, that the gate delays do not have normal dstrbutons snce the delay of a gate s a non-lnear functon of the devce length. In ths paper, we compute the two components L nter and L ntra as follows. The total devce length varaton L total s typcally well characterzed durng process development and the mean and sgma of L total s avalable from the spce parameter fle. The statstcal parameters of L nter and L ntra are typcally not drectly measured durng process development. Therefore, we analyzed devce length measurements from test de on 8 manufactured wafers. Each test de conssted of 378 test structures coverng 63 dfferent test stes wth 6 dfferent structures per test ste for a total of 17688 devce length measurements. We computed the ntra de standard devaton for each type of structure on each de and set the standard devaton of L ntra equal ther average. Snce L ntra represents a devce length devaton from the chp mean, L ntra has a mean of zero. Gven the dstrbutons of L total and L ntra, the standard devaton of the nterde varaton s computed from the followng equaton: σ 2 Ltotal = σ 2 Lnter + σ 2 Lntra (EQ 2) page 2
3 INTER- AND INTRA-DIE ANALYSIS METHOD We have modeled the total devce length as the sum of two ndependent random varables. Our objectve s to obtan the dstrbuton of the path delay D p resultng from the varaton of the total devce length of the ndvdual gates n the path, D p = D ( L nter + L ntra, ) (EQ 3) where D s the delay of gate as a functon of ts devce length and the sum s taken over all gates of a path. The path delay D p s a random varable. However, computng ts dstrbuton s dffcult snce D s a non-lnear functon that cannot be accurately expressed n closed form. One method for computng the dstrbuton of D p s through Monte-Carlo smulaton. However, snce each teraton of Monte Carlo nvolves spce smulaton of the entre crcut path, ths wll have unacceptable run tme. We therefore make the followng smplfyng assumpton: D (L nter + L ntra, ) = D (L nter ) + D ( L ntra, ), (EQ 4) where D (L ntra, ) s the change of gate delay due to a small change n devce length. In other words, the gate delay of the sum of nterand ntra-de devce lengths s approxmated by the sum of the delay of the nter- and ntra-de varatons. Note that D s assumed to be ndependent of L nter whch s an approxmaton that s vald f L ntra, s small compared to L nter. The assumpton of EQ4 allows us to compute D (L nter ) and D ( L ntra, ) ndependently and then combne them to obtan the total path delay dstrbuton D p, as follows: D p = D ( L nter ) + D ( L ntra, ), (EQ 5) We dscuss the computaton of the two components, = D ( L nter ) and D pntra, = D ( L ntra, ) D pnter n the followng two Sectons. 3.1 Inter-de varablty analyss To compute the delay due to nter-de varaton we need to compute, = D ( L nter ), as functon of the nter-de devce D pnter length. Snce all gate delays D (L nter )nd p,nter share a sngle random varable, t can be effcently computed through enumeraton of the dstrbuton of the L nter. We enumerate dfferent possbltes from the worst case to the best case process corners, and compute the path delay D p,nter for each case. The dstrbuton of D p,nter s then computed by consderng the probablty of the selected devce length from L nter and ts resultng path delay for each enumeraton. In our experments, dscretzaton of L nter nto 2 devce lengths was suffcent to obtan a hgh level of accuracy. Ths requres smulatng each path 2 tmes, whch s a relatvely low cost for computng D p,nter. 3.2 Intra-de varablty analyss D pntra The path delay varaton due to ntra-de devce length varaton, = D ( L ntra, ) s a functon of multple ndependent random varables. Therefore, the number of smulatons requred for computng D p,ntra through enumeraton s m n, where m s the num- ber dscretzatons of L ntra, and n s the number of gates n the path. Even for paths consstng of a few gates, ths s therefore computatonally nfeasble. We therefore make the second smplfyng assumpton, namely that D ( L ntra, ) can be approxmated lnearly as follows: D ( L ntra, ) = D L ntra, L ntra,, (EQ 6) for small values of L ntra,, where the senstvty of the delay wth D respect to devce length s computed at the nomnal devce L ntra, length. The smplfcaton of EQ6 allows us to compute the change of path delay D p,ntra due to ntra-de devce length varaton analytcally and effcently usng precomputed delay senstvtes. When computng D p,ntra the dependence of the delay of gate on gate nput load of ts fanout gate +1 must be consdered, whch s a functon of the devce length L ntra,+1. Smlarly, the delay of gate s dependent on ts nput slope, whch s a functon of all devce lengths L ntra,j, where gate j<precedes gate n the path. We therefore extend the lnear assumpton of EQ6 to the change of a gate delay and output slope due to nput slope and output load and formulate the computaton of D p,ntra as follows. The change n path delay D p,ntra s the sum of the ndvdual gate delay changes D, where each of the gate delay changes and ther correspondng output slope changes are a functon of the change n output slope of the precedng gate ( S -1 ), the change n nput load of the succeedng gate ( Cl +1 ), and the ntra-de devce length: D = f ( Cl + 1, S 1, L ntra, ) (EQ 7) S = f ( Cl + 1, S 1, L ntra, ) (EQ 8) The change n delay, slope and nput capactance of a sngle gate s approxmated as a sum of products of the senstvtes and the change n the parameter values: D D D D = S S 1 + L 1 L ntra, + Cl Cl + 1 + 1 S S S S = S S 1 + L 1 L ntra, + Cl Cl + 1 + 1 Cl Cl = L L ntra, (EQ 9) (EQ 1) (EQ 11) The seven basc senstvtes of delay and slope wth respect to nput slope, output load and devce length and the senstvty of gate nput load wth respect to devce length are precomputed for each gate over a range of output load and nput slope condtons. In ths paper, we computed the senstvtes numercally, although methods for drectly computng these senstvtes durng crcut smulaton are also possble. These basc senstvtes are then stored n tables and are then accessed durng the computaton of D p,ntra for a partcular path usng lnear nterpolaton of the stored values n the table. We then substtute EQ11 n EQ1 and EQ1 n EQ9 to obtan an expresson of D as a functon of basc senstvtes and ntra-de devce length varatons. Note that D s a functon of all ntra-de devce lengths j, where j + 1, due to the recursve dependence of S on S -1. The change n delay of gate therefore depends on the ntra-de devce length of the gate tself, the succeedng gate and all precedng gates and s expressed as a lnear functon of these ntrade devce lengths. The delay change coeffcents of ths functon are effcently computed for all gates n the path usng a sngle traversal page 3
of the path usng the basc seven senstvtes. We then collect all coeffcents of gate delays wth respect to each ntra-de devce length and express the total change n path delay D p,ntra as follows:, = ( K L ), (EQ 12) D pntra where K s the coeffcent of total path delay change due to ntra-de devce length L at gate.gven the mean µ and the standard devaton σ for ntra-de devce length L wth normal dstrbuton and the coeffcents K, we can compute mean and standard devaton of the probablty dstrbuton for D p,ntra drectly usng the followng standard equatons: µ Dpntra = K, µ 2 σ Dpntra, = K 2 2 ( σ ) (EQ 13) (EQ 14) Gven precharacterzed senstvtes, the fnal computaton of the dstrbuton of D p,ntra s performed very effcently and requres only a sngle traversal of the path. To valdate the accuracy of the proposed, we compare the dstrbuton of D p,ntra computed through the proposed analytcal wth that obtaned through Monte Carlo smulaton n Secton 5. 3.3 Combned analyss and comparson to tradtonal After computng the two components of path delay varaton, D p,nter (L nter ) and D p,ntra ( L ntra, ) (EQ4), we compute dstrbuton of the total path delay D p. Snce L nter and L ntra, are ndependent random varables, ths nvolves the convoluton of the two dstrbutons. However, snce D p,nter s not normal, the convoluton can not be preformed analytcally and must be performed numercally. Ths s performed by dscretzng the two dstrbutons and then takng ther convoluton numercally. The total path delay dstrbuton s agan valdated usng Monte Carlo smulaton n Secton 5. We also compute the path delay dstrbuton when we treat the total varaton as nter-de varaton and the ntra-de varaton as zero, σ Lnter = σ Ltotal σ Lntra =. We agan use enumeraton of the dstrbuton of L nter to obtan the path delay dstrbuton. We refer to ths delay dstrbuton as the tradtonal delay dstrbuton, snce tradtonally all varatons are treated as nter-de varatons and computed usng case analyss. We compare the delay dstrbuton obtaned wth the proposed to the tradtonal delay dstrbuton n Secton 5. 4 MODEL AND ANALYSIS OF SPATIAL CORRELATIONS We propose a new model for spatal correlaton of ntra-de devce length varaton. We frst dvde the area of the de nto regons usng a mult-level quad-tree parttonng, as shown n Fgure 1. For each level l, the de area s parttoned nto 2 l -by-2 l squares, where the frst or top level has a sngle regon for the entre de and the last or bottom level k has 4 k regons. We then assocate an ndependent random varable L l,r wth each regon (l, r) to represent a component of the total ntra-de devce length varaton. The varaton of a gate s then composed of a sum of ntra-de devce length components 2,1 1,1 2,2 2,3 2,5 2,4 2,9 2,6,1 1,2 2,7 1,3 2,1 2,11 2,8 2,13 Fgure 1. Spatal correlatons 2,12 1,4 2,14 2,15 2,16 L l,r, where level l ranges from to k and the regon r at a partcular level s the regon that ntersects wth the poston of gate on the de. For the gate n regon 2,1 n Fgure 1, the components of ntrade devce length varaton would be L,1, L 1,1 and L 2,1. The ntra-de devce length components are defned such that the sum of all random varables L l,r assocated wth a gate s equal to L ntra,: L ntra, = L lr, < l < k, r ntersects (EQ 15) Gates that le wthn close proxmty of each other wll have many common ntra-de devce length components resultng n a strong ntra-de length correlaton. Gates that le far apart on a de share few common components and therefore have weaker correlaton. Fgure 1 shows an example of a de wth 3 levels of parttonng resultng n 16 regon at the bottom level. Snce the number of regons at the bottom level grows as 4 k t s possble to obtan a fne parttonng of the de wth only a moderate number of levels. Note also that length L,1 assocated wth the regon of at the top level of the herarchy s equvalent to the nter-de devce length L nter snce t s shared by all gates on the de. We can control how quckly the spatal correlaton dmnshes as the separaton between two gates ncreases by correctly allocatng the total ntra-de devce length varaton among the dfferent levels. If the total ntra-de varance s largely allocated to the bottom levels, and the regons at top levels have only a small varance, there s less sharng of devce length varaton between gates that are far apart and the spatal correlaton wll dmnsh quckly. The results wll yeld results that are close to uncorrelated ntra-de analyss. On the other hand, f the total ntra-de varance s predomnantly allocated to the regons at the top levels of the herarchy, then even gates that are wdely spaced apart wll stll have sgnfcant correlaton. Ths wll yeld results that are close to the tradtonal where all gates are perfectly correlated and the ntra-de devce length varaton s zero. The proposed model s therefore flexble and can be easly ft to measured devce length data. Also, t s straghtforward to page 4
extend the model to nclude topologcal and structural correlatons, such as gate orentaton. We llustrate the spatal correlaton model for the three gates shown n Fgure 1 n regons (2,1), (2,4) and (2,15). The ntra-de devce length varaton of these gates s the sum of devce length varaton components assocated wth regons that the gate les n leadng to the followng equatons: L ntra, 1 = L 21, + L 11, + L 1, (EQ 16) L ntra, 2 = L 24, + L 11, + L 1, (EQ 17) = + + (EQ 18) L ntra, 3 L 215, L 14, L 1, We can observe from the ntra-de devce length equatons that gates 1 and 2 are strongly correlated, as they share the common varables L 1,1 and L,1. On the other hand, gates 1 and 3 are more weakly correlated as they share only the common varable L,1. The change n delay due to ntra-de devce length varaton for these gates can be expressed as the product ther ntra-de devce length components wth ther respectve coeffcents of the total path delay change. Usng equaton EQ12, we get the followng equatons: D 1 = K 1 ( L 21, + L 11, + L 1, ) (EQ 19) D 2 = K 2 ( L 24, + L 11, + L 1, ) (EQ 2) D 3 = K 3 ( L 215, + L 14, + L 1, ) (EQ 21) Summng up the D s n EQ19 through EQ21, we get the change n the path delay D p,ntra due to spatally correlated ntra-de devce length varaton as follows: D pntra, = K 1 ( L 21, ) + K 2 ( L 24, ) + K 3 ( L 215, ) + ( K 1 + K 2 ) L 11, + K 3 ( L 14, ) + ( K 1 + K 2 + K 3 ) L 1, (EQ 22) We then compute the path delay dstrbuton n the same way as the ntra-de varablty analyss usng equatons EQ13 and EQ14. 5 EXPERIMENTAL RESULTS We apply our to crtcal paths extracted from an ndustral, hgh performance desgn. The Spce smulatons were performed usng a process wth.18mcron nomnal devce length. The standard devaton used for ntra-de varablty was based on measurements from a test chp and was 4.41% of the nomnal devce length. The total varablty had a standard devaton of 6.6% of nomnal. The standard devaton of nter-de devce length was computed usng EQ2 and was 4.97%. Normal dstrbutons were used for all varatons. The proposed Inter- and Intra-de analyss methods were mplemented as well as the tradtonal. Also, Intra-de analyss wth spatal correlatons was mplemented usng a 6 level herarchy. The varance of the ntra-de varablty components at each level were obtaned from test chp measurements. In Fgure 2, we show a plot of the path delay probablty densty functon of path p2 for both the tradtonal and our proposed method consderng ntra- and nter-de devce length varatons. The means of both these dstrbutons are algned at 2493.1. The dstrbuton obtaned by our s more narrow than the tradtonal, ndcatng less varablty and a smaller standard devaton. The 3-sgma delay pont wth our s also smaller than that obtaned wth the tradtonal, whch means that the path delay dstrbuton s less pessmstc wth our. prob cdf.3.25.2.15.1.5 Our Tradtonal 16 18 2 22 24 26 28 3 32 34 Fgure 2. Comparson of probablty densty functon for tradtonal and proposed Fgure 3 shows the same comparson, but nstead of a probablty 1.9.8.7.6.5.4.3.2.1 Our conv (nter,ntra) densty functon, we have plotted the cumulatve dstrbuton functons (cdf) of both the es. A cdf at any tme pont, shows the probablty of an event occurrng at or before that tme pont. The fgure shows a sgnfcant dfference between the es at the 99% pont. In Table 1, we show the path characterstcs such as the number of gates, the mean delay of the path, the standard devaton and 3-sgma ponts of the path delay dstrbuton usng our and the tradtonal. The percentage reducton n the standard devaton and 3-sgma delay ponts obtaned wth our are shown n Table 1. The varablty usng the proposed s reduced by 27.2% on average, compared to the tradtonal analyss. The percentage reducton n the 3-sgma delay ponts s 4.46% on average. In Fgure 4, we show the comparson between the results obtaned usng our proposed analytcal and Monte Carlo smulaton for ntra-de delay varablty analyss of path p2. The plot shows a close match between the analytcal and the Monte Carlo smulaton. In Fgure 5 we compare the total path delay probablty dstrbuton for the two es for path p2. The mean and sgma of the dstrbuton usng Monte-Carlo smulaton were 2487 and 17 whch s matched closely by the mean and sgma obtaned usng our analytcal, whch were 2493 and 112. Tradtonal 16 18 2 22 24 26 28 3 32 34 Fgure 3. Cumulatve dstrbuton functon for tradtonal and proposed es page 5
prob.9.8.7.6.5.4.3.2.1 analytcal montecarlo 2 15 1 5 5 1 15 2 Fgure 4. Comparson of Monte Carlo smulaton and analytcal for ntra-de delay varablty Table 2. Path delay dstrbuton wth dfferent spatal correlatons Crtcal paths sgma for D p,ntra () (uncorrelated) sgma for D p,ntra () (correlated) %ncrease n sgma 3 sgma-pt wth our (correlated) () Correlated % red p1 43.5 68.5 57.4% 2519.7 3.3% p2 45.1 73.1 62.1% 2853. 3.3% p3 6. 114.6 91.% 568.8 3.9% p4 56.8 19.6 93.% 4568.8 4.5% p5 6.9 115.8 9.% 4797.2 4.1% p6 48.4 89.8 85.5% 4515.1 4.4% p7 55.4 13.1 86.1% 4437.1 3.7% ues are for the ntra-de path delay dstrbuton wthout any spatal correlaton. We then show the sgma values for the ntra-de path delay wth correlatons, calculated usng our model for spatal correlaton. The varablty s ncreased on average by 8.7% when spatal correlaton s consdered, compared to uncorrelated analyss. We then show the 3-sgma delay values for the total path delay dstrbuton, and report the percentage reducton wth spatally correlated analyss over the tradtonal analyss whch was 3.88% on average. prob.3.25.2.15 Monte Carlo Our 6CONCLUSIONS In concluson, we have presented a new method for computng the delay dstrbuton of crtcal paths that consders nter- and ntra-de varatons. We propose a model for nter- and ntra-de devce length varaton and show how the delay dstrbuton can be effcently computed usng delay senstvtes. We also propose a new model for spatal correlatons that can accurately capture the effect of ntra-de spatal correlatons. The methods were tested on paths from a hgh performance mcroprocessor. Monte Carlo smulaton was used to demonstrate the hgh accuracy of the proposed..1.5 Fgure 5. Comparson of Monte Carlo smulaton and analytcal fo total delay varablty Table 1. Results of proposed and tradtonal crtcal paths 16 18 2 22 24 26 28 3 32 34 No. of gates mean delay () standard devaton () tradtonal Our %red tradtonal 3sgma delay () Our %red p1 14 2188.3 139 13 26% 265.7 2498. 4.1% p2 12 2493.1 152 112 26% 295.5 283.1 4.1% p3 25 4449.3 276 199 28% 5276.7 546. 4.4% p4 32 3935.6 283 23 28% 4785.8 4546.3 5.% p5 23 4177.1 276 199 28% 54.3 4774.5 4.6% p6 43 3922. 266 191 28% 4721.9 4494.6 4.8% p7 2 3895.9 237 172 27% 466.8 4412.3 4.2% ACKNOWLEDGEMENTS Ths research was supported by SRC contract 21-HJ-959 and NSF grant CCR-25227. REFERENCES [1] M. Orshansky, L. Mlor, P. Chen, K. Keutzer, C. Hu, Impact of systematc spatal ntra-chp gate length varablty on performance of hgh-speed dgtal crcuts, ICCAD 2, pp. 62-67. [2] V.Mehrotra, S.L.Sam, D.Bonng, A.Chandrakasan, R.Vallshayee, S.Nassf A methodology for modellng the effects of systematc wthn-de nterconnect and devce varaton on crcut performance. DAC 2. [3] S.Devadas; H.F.Jyu; K.Keutzer; S.Malk Statstcal tmng analyss of combnatonal crcuts, ICCD 1992 pp. 38-43 [4] R.B. Brawhear, N. Menezes, C. Oh, L. Pllage, R. Mercer, Predctng crcut performance usng crcut-level statstcal tmng analyss European Desgn and Test Conference, 1994. [5] M. Berkelaar, Statstcal Delay Calculaton, a Lnear Tme Method, Proceedngs of TAU 97, Austn, TX, December 1997 [6] J.J Lou, K.T. Cheng, S. Kundu, A. Krstc, Fast Statstcal Tmng Analyss By Probablstc Event Propagaton, DAC 21 [7] M. Orshanshy, K. Keutzer, A general probablstc framework for worst-case tmng analyss, Proc. DAC 22. [8] A. Gattker, S.Nassf, R.Dnakar, C.Long Tmng Yeld Estmaton from Statc Tmng Analyss,Proc. ISQED 21 In Table 2, we show the results of the ntra-de varablty analyss usng spatal correlatons. The uncorrelated standard devaton val- page 6