Efficient Power Conversion Corporation
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1 The egan FET Journey Continues Using egan FETs for Envelope Tracking Buck Converters Johan Strydom Efficient Power Conversion Corporation EPC - The Leader in egan FETs PELS
2 Agenda Overview of Envelope Tracking Why egan FETs for Envelope Tracking Maximizing Device Performance Experimental Results Current Limitations Summary Q & A egan is a registered trademark of Efficient Power Conversion Corporation EPC - The Leader in egan FETs PELS
3 Overview of Envelope Tracking EPC - The Leader in egan FETs PELS
4 Why Envelope Tracking? Exabytes per Month Source: Cisco VNI Mobile Data Traffic Forecast % Compound annual growth rate (CAGR) Same average Reference: Nujira.com website EPC - The Leader in egan FETs PELS
5 Effect of PAPR Average Power Peak Power Fixed supply PAPR = 0dB Peak efficiency up to 65% Average efficiency only 25% Increasing PAPR Output Probability Output Power (dbm) EPC - The Leader in egan FETs PELS
6 Effect of Envelope Tracking Average efficiency ~50% (incl. ET) Only 1/3 the losses Envelope Tracking 60 ~100MHz BW ET for 4G LTE Output Probability Average Power Output Power (dbm) EPC - The Leader in egan FETs PELS
7 Hybrid ET Implementation Improvement in switching device performance buys: Improves overall ET efficiency Increases Switcher stage bandwidth Simplifies Linear stage design / Removes it entirely? Increase system BW which increases RFPA fidelity Kimball, Don, et al. "50% PAE WCDMA basestation amplifier implemented with GaN HFETs." Compound Semiconductor Integrated Circuit Symposium, CSIC'05. IEEE. IEEE, EPC - The Leader in egan FETs PELS
8 Why egan FETs for Envelope Tracking EPC - The Leader in egan FETs PELS
9 Idealized Switching V IN T CR T VF V DS I DS V V GS I ON V PL V TH α α t EPC - The Leader in egan FETs PELS
10 Hard-Switching Figure of Merit FOM HS =(Q GD +Q GS S2) R DS(on) (pc Ω) EPC Gen 4 EPC Gen 2 Vendor A Vendor B Vendor C Vendor D Vendor E 6.1x 3.5x 8.5x Drain-to-Source Voltage (V) V DS =0.5 V DSS, I DS =20 A EPC - The Leader in egan FETs PELS
11 High Frequency egan FETs EPC Part No. BV (V) Max. R DS(ON) Min. Typical Charge (pc) (mω) Peak Id (A) (V GS = 5V, (Pulsed, 25 o C, I D = 0.5 A) T pulse = 300 µs) Q G Q GD Q GS Q OSS Q RR Typical Capacitance (pf) (V DS = 20 V; V GS = 0 V) C ISS C OSS C RSS EPC EPC EPC EPC EPC EPC EPC EPC egan is a registered trademark of Efficient Power Conversion Corporation EPC - The Leader in egan FETs PELS
12 Hard Switching FOM EPC - The Leader in egan FETs PELS
13 dv/dt Turn-on Immunity Q GS1 >Q GD 20V 40V Q GS1 Q GD EPC8004 egan FET EPC - The Leader in egan FETs PELS
14 Maximizing Device Performance EPC - The Leader in egan FETs PELS
15 Common Source Inductance V IN T CR T VF V IN T CR T VF I ON I ON I DS V DS I DS V V DS GS V GS V PL V TH α α t EPC - The Leader in egan FETs PELS
16 Drain Packaging Evolution Gate Source Power Loss (W) egan FET SO-8 LFPAK DirectFET LGA Device Loss Breakdown 82% 18% Package Die 73% 27% 47% 53% V IN =12V V OUT =1.2V I OUT =20A F S =1MHz 18% 82% SO-8 LFPAK DirectFET LGA Efficiency (%) SO-8 LFPAK DirectFET LGA Switching Frequency (MHz) EPC - The Leader in egan FETs PELS
17 Converter Parasitics C in T SR L S : Common Source Inductance L Loop : High Frequency Power Loop Inductance Power Loss(W) Power Loss vs Parasitic Inductance Ls L Loop Parasitic Inductance (nh) V IN =12 V, V OUT =1.2 V, f sw =1 MHz, I OUT = 20 A EPC - The Leader in egan FETs PELS
18 EPC8XXX Package Drain 200 X2 Sub Gate Return Source S x All dimensions in µm EPC - The Leader in egan FETs PELS
19 Low Parasitic Layout Top Layer Vias to next layer To BUS caps Switch node Supply Return Source S Drain Sub PELS 2014 Gate Current orthogonal to drain current Vias to next layer Ground Source EPC - The Leader in egan FETs Sub Return Bottom Gate Gate Top Gate Gate Drain S 19
20 Low Parasitic Layout First Inner Layer Optimum power loop return To gate drive Drain Sub Optimum gate loop return Gate Return Source S To gate drive Drain Sub Optimum gate loop return Gate Return Source S EPC - The Leader in egan FETs PELS
21 EPC8000 Series Improvements Reduce active area for lower power / higher frequency operation Minimize Hard Switching Figure of Merit Complete dv/dt turn-on immunity Separate gate and power loops Minimize power loop inductance Minimize gate loop inductance EPC - The Leader in egan FETs PELS
22 Experimental Results EPC - The Leader in egan FETs PELS
23 ET Prototype Board 2X, SO-8 footprint Bus caps LM5113 EPC80XX EPC80XX EPC - The Leader in egan FETs PELS
24 20 V BUS, 10 MHz, 4 A Switching EPC - The Leader in egan FETs PELS ,
25 Efficien ncy 95% 93% 91% 89% 87% 85% 83% 81% 79% 77% 75% 73% 71% Near >4:1 step down ratio 15 V IN to 3.3 V OUT, 10 MHz Output Power (W) EPC8007 EPC - The Leader in egan FETs PELS Power Los ss (W)
26 42 V IN at 1 A OUT No measureable overshoot dv/dt interval 75V/ns slew rate di/dt interval Rise time ~1.0 ns Total switching time ~1.2 ns 2 ns/div and 10 V/div, 1 GHz 100:1 1pF TM probe EPC - The Leader in egan FETs PELS ,
27 42 V IN, 20 V OUT, 10 MHz Conduction Switching C OSS Additional losses EPC8005 EPC - The Leader in egan FETs PELS
28 Current Limitations EPC - The Leader in egan FETs PELS
29 Parasitic Losses Bootstra ap diode Reverse recovery charge V DD IC capacitance Level Shift V DD Switch-node rising edge half-bridge driver EPC - The Leader in egan FETs PELS
30 No-load Switching 10 MHz switching, no load, large dead-time 10 V/div, 100 ma/div, 10 ns/div Expected commutation based on egan FET C OSS Initially slow rising edge Actual voltage commutation slopes are different, even though currents are the same EPC - The Leader in egan FETs PELS
31 Loss Breakdown 10 MHz switching, no load, large dead-time 10 V/div, 100 ma/div, 10 ns/div Switch-node voltage Bootstrap Q RR Actual commutation based on total C OSS including IC capacitance EPC - The Leader in egan FETs PELS
32 42 V IN, 20 V OUT, 10 MHz Conduction Switching C OSS C OSS Gate Driver Switching Q RR Bootstrap diode EPC - The Leader in egan FETs PELS
33 egan FET Limited Efficiency Calculated efficiency improvement EPC - The Leader in egan FETs PELS
34 Summary New devices enable higher switching frequencies Switching 42 V, 40 W at 10 MHz at 89% possible. Driver parasitics limit performance light load losses can be cut in half, and full load losses can be reduced by 25% EPC - The Leader in egan FETs PELS
35 Thank you! Questions? EPC - The Leader in egan FETs PELS
36 The end of the road for silicon.. is the beginning of the egan FET journey! EPC - The Leader in egan FETs PELS
Driving egan FETs in High Performance Power Conversion Systems
The egan FET Journey Continues Driving egan FETs in High Performance Power Conversion Systems Alexander Lidow PhD Efficient Power Conversion Corporation EPC - The Leader in egan FETs ECS 2011 www.epc-co.com
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