CMSC22200 Computer Architecture Lecture 8: Out-of-Order Execution. Prof. Yanjing Li University of Chicago
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1 CMSC22200 Computer Architecture Lecture 8: Out-of-Order Executio Prof. Yajig Li Uiversity of Chicago
2 Lecture Outlie Exceptios ad iterrupts OoO 2
3 Exceptios ad Iterrupts Uexpected evets reuirig chage i flow of cotrol Thik of it as a special case of brach Exceptio Iteral to a thread Iterrupt e.g., udefied opcode, overflow, syscall, From a exteral source (e.g.. I/O cotroller)
4 Whe to Hadle? Exceptios Whe detected (ad kow to be o-speculative) I the 5-stage ARMv8 pipelie processor, i which stage ca we detect the followig exceptios? Divide-by-0, udefied machie code, page fault Iterrupts Whe coveiet Except for very high priority oes Power failure Machie check (error) Multiple exceptios/iterrupts ca occur at the same time Priorities ad timig behavior defied i ISA 4
5 Precise Exceptios The architectural state should be cosistet whe the exceptio/iterrupt is ready to be hadled 1. All previous istructios should be completely retired. 2. No later istructio should be retired. Retire = commit = fiish executio ad update arch. state 5
6 Complex Hardware for Precise Exceptios Pipeliig overlaps multiple istructios Could have multiple exceptios at oce I complex pipelies Multiple istructios issued per cycle Out-of-order completio Maitaiig precise exceptios is difficult!
7 Why Do We Wat Precise Exceptios? Sematics of the vo Neuma model ISA specifies it Aids software debuggig Thik about breakpoits; how useful are they if we do t have precise exceptios? Eables much easier recovery from exceptios e.g. page faults; restart from the faultig istructio after it s hadled 7
8 Providig Precise Exceptios I-order 5-stage pipelie t 0 t 1 t 2 t 3 t 4 t 5 Ist h IF PC ID EX killed Ist i Ist j IF PC+4 ID IF PC+8 killed killed Ist k Ist l IF ID IF EX ID IF WB EX ID IF Ist k is the first istructio of the exceptio hadlig routie 8
9 Hadlig Exceptios i LEGv8/ARMv8 Save PC of offedig (or iterrupted) istructio I Exceptio Lik Register (ELR) Save idicatio of the problem I Exceptio Sydrome Register (ESR) Jump to a reserved PC address, i.e., etry-poit of a commo exceptio/iterrupt hadlig routie registered by the OS
10 A Alterate Mechaism (Doe i X86) Vectored Iterrupts Hadler address determied by the cause Exceptio vector address to be added to a vector table base register (registered by the OS): Ukow Reaso: two Overflow: two : two Istructios either Deal with the iterrupt, or Jump to real hadler Still eed to remember the PC of the faultig istructio
11 Hadler Actios Read cause, ad trasfer to relevat hadler Determie actio reuired If restartable Take corrective actio use EPC to retur to program Otherwise Termiate program Report error usig EPC, cause, Exceptio/iterrupt hadlig reuires HW/SW collaboratio
12 Out-of-Order Executio
13 Motivatio: Load-Use Depedecy Cosider this seuece Reuires 1 stall LDUR X2, [X1,#20] AND X4,X2,X5 OR X8,X3,X6 Static schedulig to re-order istructios No eed to stall LDUR X2, [X1,#20] OR X8,X3,X6 AND X4,X2,X5 What if load sometimes take 100 cycles to execute? 13
14 Aother Example: Istructios w/ Variable Latecies E Iteger add F D E E E E Iteger mul E E E E E E E E FP mul W E E E E E E E E... Cache miss 14
15 Depedecy Hadlig Cosider the followig two pieces of code IMUL R3 ß R1, R2 ADD R3 ß R3, R1 ADD R1 ß R6, R7 IMUL R5 ß R6, R8 ADD R7 ß R3, R5 LD R3 ß R1 (0) ADD R3 ß R3, R1 ADD R1 ß R6, R7 IMUL R5 ß R6, R8 ADD R7 ß R3, R5 I both cases, first ADD stalls the whole pipelie! ADD caot dispatch because of depedecies Later idepedet istructios caot get executed IMUL ad LD ca take a log time Latecy of LD is ukow util rutime (cache hit vs. miss) 15
16 How to Do Better? Hardware has kowledge of dyamic evets o a peristructio basis (i.e., at a very fie graularity) Cache misses Brach mispredictios Load/store addresses Would t it be ice if hardware did the schedulig of istructios? Hardware-based dyamic istructio schedulig, eablig OOO executio Tradeoffs vs. static schedulig? 16
17 Beefits of OOO I order F D E E E E M W F D STALL E M W F Out-of-order F D E E E E M W F D F D STALL WAIT E M D E M W F D E E E E M W F D STALL E M W E M W W F D E E E E M W F D WAIT E M W IMUL R3 ß R1, R2 ADD R3 ß R3, R1 ADD R1 ß R6, R7 IMUL R5 ß R6, R8 ADD R7 ß R3, R5 Assume: IMUL: 4 Ex cycles ADD: 1 Ex cycle 15 vs. 12 cycles 17
18 Out-of-Order Executio Idea Move the depedet istructios out of the way of idepedet oes (s.t. idepedet oes ca execute) Approach Moitor the source values of each istructio Whe all source values of a istructio are available, fire (i.e. dispatch) the istructio Retire each istructio i program order Beefit Latecy tolerace: Allows idepedet istructios to execute ad complete i the presece of a log latecy operatio 18
19 Illustratio of a OOO Pipelie TAG ad VALUE Broadcast Bus F D S C H E D U L E E Iteger add E E E E Iteger mul E E E E E E E E FP mul E E E E E E E E... Load/store i order out of order i order R E O R D E R W Two humps Hump 1: reservatio statios (schedulig widow) Hump 2: reorder buffer (istructio widow or active widow) 19
20 Dyamic Schedulig: Tomasulo s Algorithm Iveted by Robert Tomasulo Used i IBM 360/91 Floatig Poit Uits Tomasulo, A Efficiet Algorithm for Exploitig Multiple Arithmetic Uits, IBM Joural of R&D, Ja Variats are used i may high-performace processors 20
21 Key Ideas of Tomasulo s Algorithm 1. Register reamig Track true depedecies by likig the cosumer of a value to the producer 2. Buffer istructios i reservatio statios util they are ready to execute (istructio claims a etry i RS after it s decoded) Keep track of readiess of source values Istructio wakes up ad dispatch to the appropriate fuctioal uit (FU) if all sources are ready If multiple istructios are awake, eed to select oe per FU a b 21
22 Register Reamig Output ad ati depedecies are ot true depedecies WHY? They exist because ot eough register ID s (i.e. ames) i the ISA The register ID is reamed to the reservatio statio (RS) etry that will hold the register s value Register ID à RS etry ID Architectural register ID à Physical register ID After reamig, RS etry ID used to refer to the register This elimiates ati- ad output- depedecies As if there are a large umber of registers eve though ISA ca oly support a small umber 22
23 Registe Reamig Usig RAT RAT: Register Alias Table (aka Register Reame Table) X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 tag value valid? Do t care 0 1 Do t care 1 1 RS etry 7 Do t care 0 Do t care 3 1 RS etry 3 Do t care 0 RS etry 13 Do t care 0 Do t care 6 1 Do t care 7 1 RS etry 4 Do t care 0 Do t care
24 Tomasulo s Machie: IBM 360/91 from memory from istructio uit FP registers load buffers store buffers operatio bus FU FU reservatio statios to memory Commo data bus 24
25 Tomasulo s Algorithm If reservatio statio ot available, stall; else Istructio + reamed operads (source value/tag) iserted ito the reservatio statio While i reservatio statio, each istructio: Watches commo data bus (CDB) for tag of its sources Whe tag see, grab value for the source ad keep it i the reservatio statio Whe both operads available, istructio ready to be dispatched Dispatch istructio to the Fuctioal Uit (FU) whe istructio is ready If multiple istructios ready at the same time ad reuire the same FU, eed logic to select oe After istructio fiishes i the FU Arbitrate for CDB Put tagged value oto CDB (tag broadcast) Register file, RS, ad RAT coected to the CDB Register cotais a tag idicatig the latest writer to the register If the tag i the register file, RS, ad RAT matches the broadcast tag, write broadcast value ito register (ad set valid bit) Reclaim reame tag (i.e., free the correspodig RS etry) 25
26 A Exercise MUL X3 ß X1, X2 ADD X5 ß X3, X4 ADD X7 ß X2, X6 ADD X10 ß X8, X9 MUL X11 ß X7, X10 ADD X5 ß X5, X11 load buffers from memory Assume ADD (4-cycle execute), MUL (6-cycle execute) Assume oe adder ad oe multiplier i HW Assume operatios are doe etirely usig registers No memory access F D E W FP registers from istructio uit store buffers operatio bus FU FU reservatio statios to memory Commo data bus 26
27 Drawig Template MUL X3 ß X1, X2 ADD X5 ß X3, X4 ADD X7 ß X2, X6 ADD X10 ß X8, X9 MUL X11 ß X7, X10 ADD X5 ß X5, X11 v? tag val X1 X2 X3 a r X4 b t X5 c s X6 d v X7 X8 X9 X10 ADD MUL X11 27
28 Cycle 1 MUL X3 ß X1, X2 ADD X5 ß X3, X4 ADD X7 ß X2, X6 ADD X10 ß X8, X9 MUL X11 ß X7, X10 ADD X5 ß X5, X11 F v? tag val X1 1 * 1 X2 1 * 2 X3 1 * 3 a r X4 1 * 4 b t X5 1 * 5 c s X6 1 * 6 d v X7 1 * 7 X8 1 * 8 X9 1 * 9 X10 1 * 10 ADD MUL X11 1 * 11 28
29 Cycle 2 MUL X3 ß X1, X2 ADD X5 ß X3, X4 ADD X7 ß X2, X6 ADD X10 ß X8, X9 MUL X11 ß X7, X10 ADD X5 ß X5, X11 F D F v? tag val X1 1 * 1 X2 1 * 2 X3 0 r * a r 1 * 1 1 * 2 X4 1 * 4 b t X5 1 * 5 c s X6 1 * 6 d v X7 1 * 7 X8 1 * 8 X9 1 * 9 X10 1 * 10 ADD MUL X11 1 * 11 29
30 Cycle 3 MUL X3 ß X1, X2 ADD X5 ß X3, X4 ADD X7 ß X2, X6 ADD X10 ß X8, X9 MUL X11 ß X7, X10 ADD X5 ß X5, X11 F D E F D F MUL (i RS etry r) starts to execute sice both operads are valid v? tag val X1 1 * 1 X2 1 * 2 X3 0 r * a 0 r * 1 * 4 r 1 * 1 1 * 2 X4 1 * 4 b t X5 0 a * c s X6 1 * 6 d v X7 1 * 7 X8 1 * 8 X9 1 * 9 X10 1 * 10 ADD MUL X11 1 * 11 30
31 Cycle 4 MUL X3 ß X1, X2 ADD X5 ß X3, X4 ADD X7 ß X2, X6 ADD X10 ß X8, X9 MUL X11 ß X7, X10 ADD X5 ß X5, X11 F D E E F D -- F D F ADD (i RS etry a) waits sice is ot valid v? tag val X1 1 * 1 X2 1 * 2 X3 0 r * a 0 r * 1 * 4 r 1 * 1 1 * 2 X4 1 * 4 b 1 * 2 1 * 6 t X5 0 a * c s X6 1 * 6 d v X7 0 b * X8 1 * 8 X9 1 * 9 X10 1 * 10 ADD MUL X11 1 * 11 31
32 Cycle 5 MUL X3 ß X1, X2 ADD X5 ß X3, X4 ADD X7 ß X2, X6 ADD X10 ß X8, X9 MUL X11 ß X7, X10 ADD X5 ß X5, X11 F D E E E F D F D E F D F ADD (i RS etry b) starts to execute v? tag val X1 1 * 1 X2 1 * 2 X3 0 r * a 0 r * 1 * 4 r 1 * 1 1 * 2 X4 1 * 4 b 1 * 2 1 * 6 t X5 0 a * c 1 * 8 1 * 9 s X6 1 * 6 d v X7 0 b * X8 1 * 8 X9 1 * 9 X10 0 c * ADD MUL X11 1 * 11 32
33 Cycle 6 MUL X3 ß X1, X2 ADD X5 ß X3, X4 ADD X7 ß X2, X6 ADD X10 ß X8, X9 MUL X11 ß X7, X10 ADD X5 ß X5, X11 F D E E E E F D F D E E F D E F D F ADD (i RS etry c) starts to execute v? tag val X1 1 * 1 X2 1 * 2 X3 0 r * a 0 r * 1 * 4 r 1 * 1 1 * 2 X4 1 * 4 b 1 * 2 1 * 6 t 0 b * 0 c * X5 0 a * c 1 * 8 1 * 9 s X6 1 * 6 d v X7 0 b * X8 1 * 8 X9 1 * 9 X10 0 c * ADD MUL X11 0 t * 33
34 Cycle 7 MUL X3 ß X1, X2 ADD X5 ß X3, X4 ADD X7 ß X2, X6 ADD X10 ß X8, X9 MUL X11 ß X7, X10 ADD X5 ß X5, X11 v? tag val F D E E E E E F D F D E E E F D E E F D -- F D MUL (i RS etry t) waits Pay attetio to register reamig removig WAW (x5 is reamed to a ad the d) X1 1 * 1 X2 1 * 2 X3 0 r * a 0 r * 1 * 4 r 1 * 1 1 * 2 X4 1 * 4 b 1 * 2 1 * 6 t 0 b * 0 c * X5 0 d * c 1 * 8 1 * 9 s X6 1 * 6 d 0 a * 0 t * v X7 0 b * X8 1 * 8 X9 1 * 9 X10 0 c * X11 0 t * ADD MUL 34
35 Cycle 8 MUL X3 ß X1, X2 ADD X5 ß X3, X4 ADD X7 ß X2, X6 ADD X10 ß X8, X9 MUL X11 ß X7, X10 ADD X5 ß X5, X11 F D E E E E E E F D F D E E E E F D E E E F D F D -- Broadcast results through CDB to wake up depedet istructios (check both RAT ad RS) v? tag val X1 1 * 1 X2 1 * 2 X3 0 r * a 0 r * 1 * 4 r 1 * 1 1 * 2 X4 1 * 4 b 1 * 2 1 * 6 t 0 b * 0 c * X5 0 d * c 1 * 8 1 * 9 s X6 1 * 6 d 0 a * 0 t * v X7 0 b * X8 1 * 8 X9 1 * 9 X10 0 c * ADD MUL X11 0 t * 35
36 Cycle 9 MUL X3 ß X1, X2 ADD X5 ß X3, X4 ADD X7 ß X2, X6 ADD X10 ß X8, X9 MUL X11 ß X7, X10 ADD X5 ß X5, X11 F D E E E E E E W F D E F D E E E E W F D E E E E F D F D Assumig 2 reg write ports ad forwardig, we ca dispatch ADD i RS etry a; also reclaim RS etries r ad b v? tag val X1 1 * 1 X2 1 * 2 X3 1 * 2 a 1 * 2 1 * 4 r 1 * 1 1 * 2 X4 1 * 4 b 1 * 2 1 * 6 t 1 * 8 0 c * X5 0 d * c 1 * 8 1 * 9 s X6 1 * 6 d 0 a * 0 t * v X7 1 * 8 X8 1 * 8 X9 1 * 9 X10 0 c * ADD MUL X11 0 t * 36
37 Cycle 10 MUL X3 ß X1, X2 ADD X5 ß X3, X4 ADD X7 ß X2, X6 ADD X10 ß X8, X9 MUL X11 ß X7, X10 ADD X5 ß X5, X11 F D E E E E E E W F D E E F D E E E E W F D E E E E W F D E F D Now we dispatch the secod MUL (i RS etry t) sice the third add fiishes v? tag val X1 1 * 1 X2 1 * 2 X3 1 * 2 a 1 * 2 1 * 4 r X4 1 * 4 b t 1 * 8 1 * 17 X5 0 d * c 1 * 8 1 * 9 s X6 1 * 6 d 0 a * 0 t * v X7 1 * 8 X8 1 * 8 X9 1 * 9 X10 1 * 17 ADD MUL X11 0 t * 37
38 Cycle 11 MUL X3 ß X1, X2 ADD X5 ß X3, X4 ADD X7 ß X2, X6 ADD X10 ß X8, X9 MUL X11 ß X7, X10 ADD X5 ß X5, X11 F D E E E E E E W F D E E E F D E E E E W F D E E E E W F D E E F D v? tag val X1 1 * 1 X2 1 * 2 X3 1 * 2 a 1 * 2 1 * 4 r X4 1 * 4 b t 1 * 8 1 * 17 X5 0 d * c s X6 1 * 6 d 0 a * 0 t * v X7 1 * 8 X8 1 * 8 X9 1 * 9 X10 1 * 17 ADD MUL X11 0 t * 38
39 Cycle 12 MUL X3 ß X1, X2 ADD X5 ß X3, X4 ADD X7 ß X2, X6 ADD X10 ß X8, X9 MUL X11 ß X7, X10 ADD X5 ß X5, X11 F D E E E E E E W F D E E E E F D E E E E W F D E E E E W F D E E E F D v? tag val X1 1 * 1 X2 1 * 2 X3 1 * 2 a 1 * 2 1 * 4 r X4 1 * 4 b t 1 * 8 1 * 17 X5 0 d * c s X6 1 * 6 d 0 a * 0 t * v X7 1 * 8 X8 1 * 8 X9 1 * 9 X10 1 * 17 ADD MUL X11 0 t * 39
40 Cycle 13 MUL X3 ß X1, X2 ADD X5 ß X3, X4 ADD X7 ß X2, X6 ADD X10 ß X8, X9 MUL X11 ß X7, X10 ADD X5 ß X5, X11 F D E E E E E E W F D E E E E W F D E E E E W F D E E E E W F D E E E E F D v? tag val X1 1 * 1 X2 1 * 2 X3 1 * 2 a 1 * 2 1 * 4 r X4 1 * 4 b t 1 * 8 1 * 17 X5 0 d * c s X6 1 * 6 d 1 * 6 0 t * v X7 1 * 8 X8 1 * 8 X9 1 * 9 X10 1 * 17 ADD MUL X11 0 t * 40
41 Cycle 14 MUL X3 ß X1, X2 ADD X5 ß X3, X4 ADD X7 ß X2, X6 ADD X10 ß X8, X9 MUL X11 ß X7, X10 ADD X5 ß X5, X11 F D E E E E E E W F D E E E E W F D E E E E W F D E E E E W F D E E E E E F D v? tag val X1 1 * 1 X2 1 * 2 X3 1 * 2 a r X4 1 * 4 b t 1 * 8 1 * 17 X5 0 d * c s X6 1 * 6 d 1 * 6 0 t * v X7 1 * 8 X8 1 * 8 X9 1 * 9 X10 1 * 17 ADD MUL X11 0 t * 41
42 Cycle 15 MUL X3 ß X1, X2 ADD X5 ß X3, X4 ADD X7 ß X2, X6 ADD X10 ß X8, X9 MUL X11 ß X7, X10 ADD X5 ß X5, X11 F D E E E E E E W F D E E E E W F D E E E E W F D E E E E W F D E E E E E E F D v? tag val X1 1 * 1 X2 1 * 2 X3 1 * 2 a r X4 1 * 4 b t 1 * 17 1 * 8 X5 0 d * c s X6 1 * 6 d 1 * 6 0 t * v X7 1 * 8 X8 1 * 8 X9 1 * 9 X10 1 * 17 ADD MUL X11 0 t * 42
43 Cycle 16 MUL X3 ß X1, X2 ADD X5 ß X3, X4 ADD X7 ß X2, X6 ADD X10 ß X8, X9 MUL X11 ß X7, X10 ADD X5 ß X5, X11 F D E E E E E E W F D E E E E W F D E E E E W F D E E E E W F D E E E E E E W F D E Now we dispatch the last ADD v? tag val X1 1 * 1 X2 1 * 2 X3 1 * 2 a r X4 1 * 4 b t 1 * 17 1 * 8 X5 0 d * c s X6 1 * 6 d 1 * 6 1 * 136 v X7 1 * 8 X8 1 * 8 X9 1 * 9 X10 1 * 17 ADD MUL X11 1 *
44 Cycle 19 MUL X3 ß X1, X2 ADD X5 ß X3, X4 ADD X7 ß X2, X6 ADD X10 ß X8, X9 MUL X11 ß X7, X10 ADD X5 ß X5, X11 F D E E E E E E W F D E E E E W F D E E E E W F D E E E E W F D E E E E E E W F D E E E E v? tag val X1 1 * 1 X2 1 * 2 X3 1 * 2 a r X4 1 * 4 b t X5 0 d * c s X6 1 * 6 d 1 * 6 1 * 136 v X7 1 * 8 X8 1 * 8 X9 1 * 9 X10 1 * 17 ADD MUL X11 1 *
45 Cycle 20 MUL X3 ß X1, X2 ADD X5 ß X3, X4 ADD X7 ß X2, X6 ADD X10 ß X8, X9 MUL X11 ß X7, X10 ADD X5 ß X5, X11 F D E E E E E E W F D E E E E W F D E E E E W F D E E E E W F D E E E E E E W F D E E E E W v? tag val X1 1 * 1 X2 1 * 2 X3 1 * 2 a r X4 1 * 4 b t X5 1 * 142 c s X6 1 * 6 d 1 * 6 1 * 136 v X7 1 * 8 X8 1 * 8 X9 1 * 9 X10 1 * 17 ADD MUL X11 1 *
46 Summary of Tomasulo s Algorithm 1. Lik the cosumer of a value to the producer Register reamig: Associate a tag with each data value Elimiates false depedecies 2. Buffer istructios util they are ready Isert istructio ito reservatio statios after reamig Reservatio statios are also referred to as issued ueues Eables the pipelie to move for idepedet ops 3. Keep track of readiess of source values of a istructio Broadcast the tag whe the value is produced Istructios compare their source tags to the broadcast tag à if match, source value becomes ready 4. Whe all source values of a istructio are ready, dispatch the istructio to fuctioal uit (FU), which ca be out-of-order Wakeup ad select/schedule the istructio 46
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