Report for Prediction Processor Graduate Computer Architecture I

Transcription

1 Report for Prediction Processor Graduate Computer Architecture I Qian Wan Washington University in St. Louis, St. Louis, MO QW2@cec.wustl.edu Abstract This report is to fulfill the partial requirement for the final project for cse/ese 560m. Prediction Processor is the final project I have done based on the research interest of applying financial decision making strategies to engineering field. Resource allocation is the special area I would like to explore the application first. Since this is a computer architecture class, a parallel proprietary architecture is proposed and implemented to accommodate the idea. All the components are developed from scratch except the register file and sram modules. Through the software algorithm design and hardware circuit design, a balancing development cycle is adopted to provide scalability, flexibility and performance. The idea of using option Black-Scholes price model as the starting point in engineering resource allocation problems hasn t been proposed before, so this is an exploration to find new equilibrium. As well as on the architecture side, new parallel comparison is discussed here for faster processing and generation of the results for future work. 1. Introduction and motivation 1.1 Option and Black-Scholes model Option, resource allocation, On December 1, 2005[1], The Options Industry Council (OIC) announced that options trading volume continued to grow in November as 149,274,804 contracts changed hands, a 29.95% increase over the Nov level of 114,869,591 contracts - the highest volume month of last year. November s trading volume is the second highest month on record, following October s 154,794,867 contracts. Average daily volume in November was 7,108,324, more than 1.6 million contracts per day better than Nov Before we start the discussion we have to get a little familiar with what an option is and what the role of Black-Scholes option price model [2] has played since its debut in U.S. November Option volumes for the last 7 years 160,000, ,000, ,000, ,000,000 80,000,000 60,000,000 40,000,000 20,000, Figure 1: The illustration of the increase of option trading volumes in busy November over the last 7 years As we can see, thousands of billions of U.S. dollars have changed hands every month on trading options, and the volume keeps breaking old records year after year. So as defined in Professor Black and Professor Scholes famous Nobel Price winning paper, an option is defined as a security giving the right to buy or sell an asset, subject to certain conditions, within a specified period of time. There is another way to interpret this hot term often heard when people join a start-up company. I feel that option is a prediction into the future about whether a event will happen within a certain period of time based on its past performance and current performance. Without certain conditions, it will be the same in predicting the change of the price of an asset normally a stock. For speculation, people either trade an asset directly, or most likely trade its option for potentially higher risks and rewards. Most option formulas are based on the Black-Scholes model. The trillion dollars influencing equation hasn t been

2 used in engineering field, and I estimated a huge potential in its much wider use in complex optimization problems in resource allocation, decision making and so on. To assist understanding my idea in using Black- Scholes option price model into engineering problems, I will introduce the call option concept first. Then I will list the assumptions. Lastly I will show the equation. All are taken from the current version of wikipedia instead of from the original paper for easier explanation. A call option is a financial contract between two parties, the buyer and the seller of this type of option. Often it is simply labeled a "call". The buyer of the option has the right but not the obligation to buy an agreed quantity of a particular commodity or financial instrument (the underlying instrument) from the seller of the option at a certain time for a certain price (the strike price). The seller (or "writer") is obliged to sell the commodity or financial instrument should the buyer so decide. The buyer pays a fee (called a premium) for this right. From the current version of wikipedia, the key assumptions of the Black-Scholes model are: The price of the underlying instrument is a geometric Brownian motion, in particular with constant drift and volatility. It is possible to short sell the underlying stock. There are no riskless arbitrage opportunities. Trading in the stock is continuous. There are no transaction costs or taxes. All securities are perfectly divisible (e.g. it is possible to buy 1/100th of a share). The risk-free interest rate is constant, and the same for all maturity dates. The formula below is for the price of a call on a stock currently trading at price S, where the option has an exercise price of K, i.e. the right to buy a share at price K, at T years in the future. The constant interest rate is r and the constant stock volatility is σ. C ( S, T ) = SN ( d 1 ) - Ke rt N( d 2 ) where d 1 = ln 2 ( S ) + ( r + ) K σ T σ T 2 d 2 = d 1 σ T. Here N is the cumulative normal distribution function. There are other option models such as binomial options model and Monte Carlo option model, however they all come later than Black-Scholes model and have traces of the Black-Scholes model. In fact, only Black-Scholes option price model has won them the Bank of Sweden Prize in Economic Sciences in Memory of Alfred Nobel, 1997 for a new method to determine the value of derivative. 1.2 Motivations of the application Based on the limited experience I have in finance field, option as a bigger and bigger arm in the financial world provides a much clearer and braver prediction for the price events in the future. It does have a few assumptions that are not realistic, such as trading in the stock is continuous and no transaction cost or taxes which are too obvious contradiction to current Wall Street rules. Especially if people carefully check each assumption, they will almost find no holding assumptions. However since my research is in motion planning, such as path planning for robotics, I found that a lot of the assumptions suits well for a robot putting in an unknown environment and trying to cover the whole area for rescue like tasks. The covered area associates with the movement of the robot can be mapped into the price. The estimated cost of guarantee that certain targeted coverage within given time can be mapped as option. Since the motion of robot can be visualized as a Brownian motion with free choice of direction. Since the covered area can shrink if considering the environment is dynamic, so the short sell concept is possible. There are no riskless arbitrage opportunities because no one can be certain. The movement is continuous until called off. There are no transaction costs or taxes luckily here. Since there are not any countable entities in the coverage area, so it can be considered perfectly divisible. Comparing to the modernly often adjusted interest rate as a control to the inflation and the economics development speed, the interest rate in motion planning, i.e. the known average total random coverage progress is fairly stable. Therefore we can apply Black-Scholes option price model much more appropriate here for cost prediction and hopefully that can guide the decision for which movement or algorithm to take next. Especially we can use the similar beautiful method they have come up

3 with the solution of the price equation, if we can find equilibrium in our models. Because a lot of commonly studied tasks are about multi-agents planning problems instead of a single robot searching an area, resource allocation strategies become a natural underlying challenge. Normally the total time spend is an optimization objective, and the less the better. On the other hand, no prior knowledge is always assumed, which is closer to reality such as disasters. Robocup rescue simulation league competition is a newer branch of the annual RoboCup competitions. This simulation competition is inspired by the earthquake happened in Kobe City, Japan. At 5:47 AM of January 17, 1995, Hanshin-Awaji Earthquake of a moment magnitude 6.9 hit 20 x 1 km area of Kobe City, Japan, directly killing over 6,432 people, and crushed houses for one-fifth of city's 1.5 million people. 530,000 buildings were damaged, and only 20% of them were usable after the earthquake. The cost for basic infrastructure damage exceeded 100 billion US dollars, and total property loss including private properties well exceeded 300 billion US dollars[3]. The following problems of information technology in an emergency were reported by researchers in Hanshin-Awaji Earthquake. 1. Insufficient supposed scale 2. Damage of Emergency Response centers and members 3. Cut and congestion of communication 4. Information isolation of civilians and volunteers 5. Insufficient information support in decision making By looking at the above real problems reported 10 years ago, we have improved dramatically on communication especially through wireless technology and the Internet. However the last and but no less important problem is insufficient information support in decision making. RoboCup Rescue Simulation Project is a challenge to solve these problems. Its main purpose is to provide emergency decision support by integration of disaster information, prediction, planning, and human interface. Participants of this competition will work with three types of rescuers after an earthquake in rescuing civilians and putting out fires in the buildings. A basic abstraction is where to send a given rescuer. Suppose we divide the map into three areas A, B and C, where we should send a rescuer is a tough decision. The overall objective is to reduce the damage as much as possible and save as many as civilians as possible. With dynamic changes of the environment and other rescuers and civilians movement, it is a very difficult task to decide a seeming easy question of where an available rescuer can go, especially if the decision should and must be a dynamic decision. What I have observed is that if I can give a close to reality estimation of the different areas rescue performance for the near future, then I can decide which area the spare rescuer can go. More importantly, as the time goes on, another decision can be make on which area currently needs more backups. The same method can be applied to the switch of algorithms or strategies used by different rescue individuals and teams. Similar as American options can be exercised earlier and the call option can bring in profits when the price of the underlying financial instrument climbs to the strike price, a specified target can be reached before the specified time length requirement finishes. This way, rescuers can be freed earlier for other critical tasks. 2. System and development 2.1 Overview Same as the Robocup rescue simulation league project, prediction processor is designed and studied here to find an innovative method to help in decision making fast and flexible. With the available technology, the software and hardware co-design system follows a new system development flow. Since FPGA provides an economical and flexible way of implementing a customer designed logic, the software algorithm can be accommodated with simpler and only necessary components to accomplish simplicity and scalability and speed. For the software and hardware components of the system, each component can be redesigned to serve the other component s need. If necessary, alternative subcomponents within software component or hardware component can be in place for flexible operation and fault tolerance consideration. The following sections will go into details about the software algorithm and the hardware design. The development process has also been described, so that the new development flow of the software and hardware co-design system can be seen more obviously.

4 2.2 Software component development The algorithm proposed here is called Progressively Adaptive Prediction (PAP). The insight gained from financial equations specifically the Black-Scholes model is that the different aspects of the historical information is smartly used here. More importantly, the historical information includes the dynamic information such as the speeding up or slowing down of progress, rather than only the static information. One important development here is that instead of using the Black-Scholes equation to directly calculate a value I have designed an equation simpler enough to help making decisions with the parameters found similar in the original Black-Scholes equation. The reason is that in general I only need to decide for example let the rescuer goes to area A gives a bigger potential than for the rescuer goes for the other areas. I do not really need to know or in a lot of cases hard to know exactly what are the values for each decision. Here the comparison logic is very important here. For a simpler example, if I am asked to pick the biggest apple among a basket of apples, I don t have to know the exact space the specific apple takes. Therefore I have the first version of PAP algorithm defined as: r : the natural spread speed of the disaster space. x : current score c : target score t * : maturity date of the prediction score t : current time 2 v : variance rate x_average: average score percentage_of_times_x_max : percentage of times closer to maximum score percentage_of_times_x_min : percentage of times closer to miminum score S : random number, also known as Surprise > 0 Then I have my own estimation for a relative option (reaching goal within specified time) pricing (cost) called Achievability Prediction: Achievability Prediction = ( log( average accelerated speed )) ( t* - t ) (1/2 + percentage_of_times_x_min) S (cx)(c3*x_average)(1+(variancerate)2+r)(times_x_max)(1/2+percentage_of_times_ x_max) Since the hardware implementation of the 5-stage pipelined processor is a simpler processor with ADD, SUBSTACT, SHIFT and other simple operations, I decide to make this algorithm even simpler, so it can be scaled easily and put onto the pipelined processors implemented before. For accurate prediction, I can use the one closer to Black-Scholes equation, and employ sampling methods in Multiplexing and Signaling to better calculate the achievability prediction. To better describe the simplifying process, I have used an example here based on the robocup rescue simulation rules: Assume based on the evaluation rule I can have V values for areas A, B and C at the end of every cycle: C1 C2 C3 C4 C5 C6 C7 C8 A B C TABLE 1: V values of areas A, B and C and the current cycle is 8, so values 23, 25 and 24 are the current V values respectively for area A, B and C. Suppose we have same target of V values as 30 in our mind. Then there are three major factors affecting the achievability: mf1: The distance from the current value to the target value. For example area B has the smallest distance as (30-25) = 5. mf2: The biggest increase for any consecutive cycles. For example area C has it from 12 to 19, the value is 7. mf3: the sum of accelerating speed, for example, to calculate only from C s first three cycles values, the speed from cycle 1 to 2 is (5-3)=2 and from cycle 2 to 3 is (7-5)=2, so the acceleration of the speed is (2-2)=0. A weighted equation of the sum of the above four mf (major factor)s is used as the simplified model: Achievability Prediction = ( w ) 3 i= 1 i mf i Now this simplified algorithm can be easily implemented on the 5-stage pipelined processor. Here w = 2 2 and w 1 1 = w3 =. 2.3 Hardware component development The goal of the hardware component is to provide a scalable design and implementation of the parallel running and comparison of multiple PAP algorithms. Here for easier illustration, three five stage pipelined

5 RISC processors are used and the accompanying comparison logic is implemented as well. The block diagram is shown here in Figure 2: Figure 3: Data path of my design of a five stage pipelined RISC processor Figure 2: Prediction processor block diagram The structure is pretty clear with scalability and flexibility in mind, and particularly with processing speedup as a key factor. The three same structured stacks of circuits at the left are the five stage pipelined RISC processor implemented according to David A. Patterson and John L. Hennessy s Computer Organization and Design Second Edition: The Hardware/Software Interface book [4]. The instruction set used here is a key subset of the MIPS DLX instruction set introduced in the above book. The branch logic is implemented differently because the ALU is taken from the implementation of earlier lab with different datasheet as the one found in the book. A closer look at the five stages pipelined RISC Processor is illustrated here at Figure 3: RISC stands for Reduced Instruction Set Computer and is a microprocessor CPU design philosophy that favors a smaller and simpler set of instructions that all take about the same amount of time to execute [5]. Pipelined structure improves instruction throughputs by overlapping the execution of different stages of several instructions. But the time it takes for the execution of the first instruction might be even longer with the addition of the pipeline registers (in shaded rectangular blocks). As often know as the center of a processor, CPU here has three bits representing 8 operations: SUBSTRACT, ADD, bit-wise OR, bit-wise AND, bitwise XOR, SHIFT A according to B s value, LESS and LESSorEQUAL. There is no MULTIPLICATION or DIVISION in this processor. The initial design was trying to implement special circuit for the earlier version of the complex PAP algorithm. However, inspired by the design logic in RISC s R(reduced) and in EPIC-Explicitly Parallel Instruction Computing s P(Parallel), the design block diagram in Figure 2 is finally chosen. Due to the limited number of operations by the ALU in the processors, weights in the simplified version of PAP are chosen to be the power of 2. Now the multiplication can be easily implemented by the SHIFT operation. Since 64-bits processing has not dominate the current processors market yet, so the hardware component is still implemented as a 32-bit system. Besides, limited sized instruction SRAM (Static Random Access Memory) and register file are implemented in the five stage pipelined processor.

6 3. Experiments and future developments 3.1 Experiment results C implementation has been done for testing for the simplified version of PAP. Using the example in section 2.2, the area C has the largest potential with value 42 in Figure 5, comparing to the other two areas. Figure 4: The comparison logic block diagram The above figure 4 shows the comparison logic for a three paralleled processors, with the leftmost three inputs coming from the write back stage of the processors running PAPs for areas A, B and C respectively. If observed carefully, it is not hard to see that the comparison logic can be connected directly from the output from ALU, i.e. one stage earlier than the write back stage. Furthermore, we can take advantage of the fact that all the components except the two provided templates (SRAM and register file) are implemented and tested thoroughly by myself. Comparison logic can be even intertwined into the five stages based on the exact form of the PAP algorithm used. As described in the section 2.1 Introduction, this is another good example of using PAP to influence the design of the hardware layout and through the use of FPGA or CLP reconfigurable logic, quasi-asic can be produced this way for multiple benefits. For FPGA a commonly asked question is why bother using hardware instead of a regular PC. In fact the distinction will be blurring soon as I predict. But still other than a practice in exploring the benefit of codesign in influencing the software algorithms (here the development of the PAP algorithms towards simplicity), true parallel execution is achieved here. The speedup is further extended by the alternative choices of implementation in the following sections. One other important feature of the co-design is that protected equations can be implemented directly into hardware components which are stronger in standing malicious attacks. Figure 5: Software test result screenshot Hardware implementation and simulation is done as well using ModelSim6.1a. FIFO model is also generated. The compassion logic and components are implemented, with the final 2-bit result telling which team has the best potential. For example the value of 11 with unsigned value 3 for area 3. Please note that through the implementation, the feasible design is as Figure 4. The synchronization of the ALU outputs from the three processors has to be considered, as shown in Figure 6. The values match those generated from the C programs. Figure 6: Hardware test result screenshot 1

7 The prediction values in register 15 of the three RISC processors are then going through the comparison logic and the output are two bits binary value as shown in Figure 7. Figure 7: Hardware test result screenshot 2 The clock cycle has been reduced to 16ns from 20ns, which translates to 62.6MHz clock speed. understanding of my long days and nights staying in the lab 115 Urbauer. In summary, without any above mentioned factors I would not be able to feel proud of finishing the five stage pipelined processor all by myself and on time. (As far as I know of no others were done by one person and on time in this class) It is a fun experience in reaching this stage with my research of applying financial equations to intelligent resource allocation. I will continue the experiments and exploration. An earlier accepted paper during this semester based on a previous new idea gives me more confidence in this research. As the AI develops, hopefully one day there will be smarter computers can pass Alan Turing s intelligent test. 5. References [1] Press Releases, December 1, 2005 OIC Announces November Volume Climbs 30% Over Year Ago Level Figure 8: Hardware test result screenshot Future developments There are potentials for fast parallel comparison circuits when there are a lot more results generated by the parallel RISC processors. I have found Kostas G. I. Harteros s Master s thesis targeting this problem[6]. Implemented model FIFO will be put into the system to accommodate streaming data inputs. Another potential for this system is to able to adjust the clock rate based on the throughput the system handles in real time to save power. 4. Acknowledgements and summary I would like to use this opportunity to thank the instructor of this course, Professor Young Cho, for great inspiration, knowledge, style and comments. I would also like to thank the TA for his patients and skillful VHDL knowledge, and I had taken him the longest time among all the students in this class. I would like to thank Joseph Lancaster, Winie Wong, and Phillip Jones for valuable comments on labs, projects, presentations. I would also like to thank my mother for tireless support, comments and [2] The Pricing of Options and Corporate Liabilities Fischer Black, Myron Scholes Journal of Political Economy, Vol. 81, No. 3 (May - Jun., 1973), pp [3] [4] Computer Organization and Design Second Edition : The Hardware/Software Interface, David A. Patterson, John L. Hennessy, August 1, 1997, ISBN: [5] [6] Kostas G. I. Harteros, Fast Parallel Comparison Circuits for Scheduling, FORTH_ICS/TR-304, March [7] Michael Attig, Sarang Dharmapurikar, and John Lockwood Implementation Results of Bloom Filters for String Matching, IEEE Symposium on Field-Programmable Custom Computing Machines, 2004 [8] Michael Attig and John Lockwood, SIFT: Snort Intrusion Filter for TCP, Syposium on High Performance Interconnects,2005 [9] [10] [11] Sarang Dharmapurikar and John Lockwood, Synthesizable design of a multi module memory controller, Technical Report WUCS-01-26, October 2002