Performance Analysis of Divide and Conquer Algorithms for the WHT
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1 Performace Aalyss of Dvde ad Coquer Algorhms for he WHT CS 50 Hgh Performace Compug Jeremy Johso Mha Furs, Pawel Hczeko, Hug-Je Huag Dep. of Compuer Scece Drexel Uversy
2 Movao O moder maches operao cou s o always he mos mpora performace merc. Effecve ulzao of he memory herarchy, ppelg, ad Isruco Level Parallelsm s mpora. Auomac Performace Tug ad Archecure Adapao Geerae ad Tes FFT, Marx Mulplcao, Expla performace dsrbuo
3 Oule WHT Algorhms WHT Package ad Performace Dsrbuo Performace Model Isruco Cou Cache
4 WHT Algorhms Recursve Ierave Geeral N ( )( ) WHT WHT IN / I WHTN / N ( ) WHT I WHT I where ( ), I WHT I WHT
5 WHT Implemeao N N * N N N M x WHT N *x x (x(b),x(bs), x(b(m-)s)) b,s Implemeao(esed loop) RN; S; for,, RR/N for j0,,r- for k0,,s- x jns k, S WHTN x jns k, S SS* N ; ( I - WHT I WHT )
6 Paro Trees Lef Recursve 3 Ierave 9 3 Rgh Recursve 3 Balaced
7 Ordered Paros There s a - mappg from ordered paros of oo (- )-b bary umbers. There are - ordered paros of
8 Oule WHT Algorhms WHT Package ad Performace Dsrbuo Performace Model Isruco Cou Cache
9 WHT Package Püschel & Johso (ICASSP 00) Allows easy mplemeao of ay of he possble WHT algorhms Paro ree represeao Tools W()small[] spl[w( ), W( )] Measure rume of ay algorhm Measure hardware eves (coupled wh PCL) Search for good mplemeao Dyamc programmg Evoluoary algorhm
10 Algorhm Comparso Recursve/Ierave Rume Rec &Bal/I Isruco Cou rao.00e00.80e00.60e00.0e00.0e00.00e E E-0.00E-0.00E E r/ rr/ lr/ bal/ WHT sze(^) Rec&I/Bes Rume Small/I Rume rao.0e0.00e0 8.00E E00.00E00.00E00 r/b r3/b /b 3/b b/b rao.0e0.00e0 8.00E E00.00E00.00E E00 I_/r r_/r 0.00E WHT sze(^) WHT sze(^)
11 Cache Mss Daa Recursve vs. Ierave Normalzed o Bes Recursve vs. Ierave.0E0.60E00 Rao Alg Tme/Bes Tme.00E0 8.00E E00.00E00.00E00 Recursve Tme Ierave Tme Rao Recursve/Ierave.0E00.0E00.00E E E-0.00E-0.00E-0 Isrucos L Daa Cache Msses L Daa Cache Msses 0.00E sze 0.00E00 Recursve vs. Bes 6.00E E00.00E E00.00E00.00E E sze Ierave vs. Bes 9.00E00 Rao Ierave/Bes 8.00E E E E00.00E E00.00E00.00E00 Isrucos L Daa Cache Msses L Cache Msses Rao Recursve/Ierave Isrucos L Daa Cache Msses L Cache Msses 0.00E sze sze
12 Hsogram ( 6, 0,000 samples) Wde rage performace despe equal umber of arhmec operaos ( flops) Peum III cosumes more ru me (more ppele sages) Ulra SPARC II spas a larger rage
13 Dyamc Programmg m Cos( T T ), where T s he opmal ree of sze. Ths depeds o he assumpo ha Cos oly depeds o he sze of a ree ad o where s locaed. (rue for IC, bu false for rume srde, sae of he cache).
14 Oule WHT Algorhms WHT Package ad Performace Dsrbuo Performace Model Isruco Cou Cache
15 WHT Implemeao N N * N N N M x WHT N *x x (x(b),x(bs), x(b(m-)s)) b,s Implemeao(esed loop) RN; S; for,, RR/N for j0,,r- for k0,,s- x jns k, S WHTN x jns k, S SS* N ; ( I - WHT I WHT )
16 Operao Cou Theorem. Le W N be a WHT algorhm of sze N. The he umber of floag po operaos (flops) used by W N s Nlg(N). Proof. By duco. ) ( ) ( N flops N flops W W
17 Isruco Cou Model IC( ) 3 α A( ) β ( ) α l L 3 l A l ( ) A() umber of calls o WHT procedure α umber of srucos ousde loops A l () Number of calls o base case of sze l α l umber of srucos base case of sze l L umber of eraos of ouer (), mddle (), ad ouer (3) loop β umber of srucos ouer (), mddle (), ad ouer (3) loop body
18 Small[].fle "s_.c".verso "0.0" gcc_compled.:.ex.alg.globl apply_small.ype apply_small: movl 8(%esp),%edx //load srde S o EDX movl (%esp),%eax //load x array's base address o EAX fldl (%eax) // s(0)r7x[0] fldl (%eax,%edx,8) //s(0)r6x[s] fld %s() //s(0)r5x[0] fadd %s(),%s // R5x[0]x[S] fxch %s() //s(0)r5x[0],s()r7x[0]x[s] fsubp %s,%s() //s(0)r6x[s]-x[0]????? fxch %s() //s(0)r6x[0]x[s],s()r7x[s]-x[0] fspl (%eax) //sore x[0]x[0]x[s] fspl (%eax,%edx,8) //sore x[0]x[0]-x[s] re
19 Recurreces leaf a 0, ) A(... ), A( ) A( l l l l l A leaves umber of where, ) ( ν ν
20 Recurreces leaf a 0, ) (..., ) ( ) (..., ) ( ) (... ), ( ) ( L L L L L L L 3...
21 Hsogram usg Isruco Model (P3) α l, α l 3, ad α l 06 α 7 β 8, β 8, ad β 0
22 Cache Model Dffere WHT algorhms access daa dffere paers All algorhms wh he same se of leaf odes have he same umber of memory accesses Cou msses for accesses o daa array Parameerzed by cache sze, assocavy, ad block sze smulae usg program races (resrc o daa vecor accesses) Aalyc formula?
23 Blocked Access 3 WHT 6 ( WHT ( WHT I 8 )( I I 8 )( I ( WHT WHT I 8 ) )( I WHT ))
24 Ierleaved Access 3 WHT 6 (( WHT ( WHT I 8 )( I I )( I 8 WHT WHT ) I ) )( I 8 WHT )
25 Cache Smulaor > W : [, [ [,[]], [3, [ [,[]], [,[]] ]]]]; > PrTree(W); 3 > T : TraceWHTRW(W,0,); T : [0,, 0,,, 3,, 3, 0,,, 3,, 5,, 5, 6, 7, 6, 7,, 5, 6, 7, 0,, 0,, 0,,, 5,, 5,, 5,, 6,, 6,, 6, 3, 7, 3, 7, 3, 7, 8, 9, 8, 9, 0,, 0,, 8, 9, 0,,, 3,, 3,, 5,, 5,, 3,, 5, 8,, 8,, 8,, 9, 3, 9, 3, 9, 3, 0,, 0,, 0,,, 5,, 5,, 5, 0, 8, 0, 8, 0, 8,, 9,, 9,, 9,, 0,, 0,, 0, 3,, 3,, 3,,,,,,,, 5, 3, 5, 3, 5, 3, 6,, 6,, 6,, 7, 5, 7, 5, 7,5] > ops(t);
26 Cache Smulaor > CacheSm(T,,,,false); > CacheSm(T,,,,false); 8 > CacheSm(T,,,,false); 88
27 Cache Smulaor 3 3 memory accesses C, A, B (80, ) C, A, B (8, 8) C, A, B (7, 88) Ierave vs. Recursve (9 memory accesses) C, A, B (8, )
28 Cache Msses as a Fuco of Cache Sze C C 3 C C 5
29 Formula for Cache Msses M(L,W N,R) Number of msses for (Ι L WHT N Ι R ) )...,,... ( leaf s a f / f ),, ( M 3 N M C W W N N W N r r N l r N
30 Closed Form M(0,W_,0) 3(-c)* k* C c, k umber of pars he rghmos c posos c 3, Ierave k 3 Balaced k Rgh Recursve 3 k
31 Performace ad Speedup Models Lear combao of IC ad Msses Coeffces deermed usg lear regresso Separae sruco classes for SIMD SIMD Add, SIMD Ld, SIMD Shuffle, Oher Esmae speedup usg sruco cous Esmae SIMD performace from speedup esmae Adrews, M., Johso, J,: Performace Aalyss of a Famly of WHT Algorhms. Parallel ad Dsrbued Processg Symposum, 007. IPDPS 007. IEEE Ieraoal (6-30 March 007) -8
32 Predced vs Acual Speedup ω 3 v 3, v, 9,
33 Performace Model Resuls ω 3 v 3, v, 9, α β Radom WHTs (Szes 9 o 9) Trag Daa,000 Radom WHTs (Szes 9 o 9) Evaluao Daa Rumes ormalzed by log()
34 Error Dsrbuo for Model ω 3 v 3,, v 9 α 0.6 β 3.0,
35 Model Classfcao Percele of Bes True Posves True Negaves Model 73.00% 99.00% % 99.00% % 99.00% % 99.00% % 98.00% % 98.00% % 95.00% Model 68.00% 99.00% % 99.00% % 98.00% % 98.00% % 98.00% % 97.00% % 95.00%
36 Summary of Resuls ad Fuure Work Isruco Cou Model m, max, expeced value, varace, lmg dsrbuo Cache Model Drec mapped (closed form soluo, dsrbuo, expeced value, ad varace) Combe models Exed cache formula o clude A ad B Use as heursc o lm search ad predc performace
Performance Analysis of Divide and Conquer Algorithms for the WHT
Performace Aalyss of Dvde ad Coquer Algorhms for he WHT Jeremy Johso Mha Furs, Pawel Hczeko, Hug-Je Huag Dep. of Compuer Scece Drexel Uversy www.spral.e Movao O moder maches operao cou s o always he mos
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