r Lf V out r Cf C out

Transcription

1 Linking the ross over frequeny and the put voltage undershoot Christophe BASSO ON Seiondutor 4, rue Paul Mesplé BP TOULOUSE Cedex - Frane In ost power supplies design exaples, it is oon to arbitrarily plae the ross over frequeny to one fifth or one tenth of the swithing frequeny. However, it is little known that the ross over frequeny atually affets the put ipedane of the onverter and a relationship atually exists between both variables. Therefore, one the apaitor has been seleted based on its operating paraeters suh as rs urrent, teperature or aeptable voltage ripple, the designer an analytially selet his ross over frequeny to ath the desired put undershoot. This artile shows how to derive the relationship whih links both paraeters and will help you to tailor the bandwidth to exatly fit your needs. A siplified buk onverter Figure represents a siplified buk onverter assoiating a square-wave generator to a low-pass filter. Both the indutor and the apaitor are affeted by ohi losses. The put ipedane of suh a network an easily be derived one the input soure is shorted: = ( sl + rlf ) rcf + sc () By inspetion, we an see that the indutor resistive path doinates the ipedane in d (L is shorted and C is open) to let the indutor enter the piture as the frequeny inreases. Then, the apaitor ipedane starts to take over until it beoes a short iruit and leaves the ipedane value to its series loss r Cf. L r Lf V r Cf A a C Figure : a siplified buk representation where the urrent soure a sweeps the put ipedane. By onneting an -A a soure to the put, we have the ability to quikly plot the put ipedane versus frequeny using a SPICE siulator. Figure portrays the obtained results. As we an see, a peaking ours at the resonant frequeny f. The axiu of this peaking an be analytially derived, as shown in Ref. []:,ax R Lf = + RLf () L Where = is the harateristi ipedane of the filter. Suh peaking is typial of a buk put C ipedane behaviour where the LC filter has been optiized to iniize the losses. This situation indues a

2 high quality oeffiient, hene a severe peaking in the ipedane graph. One of the feedbak ais is to iniize the put ipedane to redue as uh as possible the voltage drop when a load step ours. On this plot, the natural put ipedane of the filter draatially peaks at the resonant frequeny. Therefore, if we selet a ross over frequeny below the LC filter resonane, we will not have enough gain to get rid of the resonane and, despite a good phase argin, the syste will osillate. If we want to obtain a good transient response, we have to ake sure the loop gain reains high enough to tae the peaking when it ours. In other words, the ross over frequeny f ust be seleted at least three-five ties above f.. R lf R lf + f ( dbω ) plot vdb in db(volts) L C f (Hz) r Lf r Cf -6. Crossover region k k k Meg frequeny in hertz Figure : as shown by Eq. (), the ohi losses doinate the put ipedane at both extrees of the graph (f = and f = ) In Figure, if we selet a ross over region beyond the resonane, we an see an ipedane graph doinated by the put apaitor ipedane C. At the ross over frequeny, this ipedane is:, OL ( f ) π f C (3) Above the ross over frequeny, the apaitor ohi losses doinate the put ipedane of the network. To ake sure Eq. (3) rules the put ipedane alone at the ross over point, the apaitor Equivalent Series Resistor (ESR) ust be uh saller than this ipedane at the ross over frequeny. Matheatially, the following ondition ust be et: r C f π f C << (4) The final apaitor hoie, besides ripple urrent and teperature onsiderations, will also inlude a onsideration for the apaitor ESR at the seleted ross over frequeny. Closing the loop Any voltage generator an be pitured with an equivalent iruit assoiating a d soure V th and an put resistor R th, aording to Frenh telegraph engineer, Charles Thévenin (857-96). V th is evaluated by easuring the put voltage on a unloaded onverter and R th is found by easuring the put voltage differene in two loading urrent onditions. Iagine that Figure 3a depits an open-loop buk onverter using Figure approah. One loop ontrol is installed through a opensator bringing gain and phase boost as in

3 Figure 3b, the open-loop ipedane transfors into a losed-loop put ipedane whih now obeys the following law (Figure 3):, CL ( s), OL ( s) + T s ( ) (5) Where: is the open-loop put ipedane before the feedbak is applied., OL is the losed-loop put ipedane for a loop gain T( s) H( s) G( s), CL =. We now have an put ipedane whose value depends on the open-loop gain. In d, for s =, we assue a large loop gain to ensure a good d regulation. In other words, the feedbak brings the open-loop ipedane to a very low value. On the ontrary, when the frequeny inreases, the gain redues and when the ross over point is reahed, the gain no longer ats upon the put ipedane. Matheatially, this an be written as follows: s, CL ( s) li (6) li s s ( ) ( ) s s (7), CL, OL I I V th R th V, OL H(s) V =, CL V d G(s) a b Figure 3: ipleenting loop ontrol on a onverter iproves several paraeters aong whih the put ipedane. If we use a SPICE average odel and opensate a voltage-ode buk onverter, we have the possibility to a sweep its put ipedane as we did in Figure. Looking at the put ipedane graph (Figure 4), it shows what Eqs. (5)(6) predited: in the low frequeny doain, thanks to a high open-loop gain, the put ipedane reains extreely sall ( ) Lf r T but as the frequeny inreases, we start to see the indutive behaviour. Then, at the ross over point, the loop gain reahes db and both the open-loop and losedloop ipedane are alost equal to the put apaitor ipedane given by Eq. (3).

4 T(s) Plot vdb#b, vdb, vdberr in db( vo lts) 5.,OL f ,CL,CL,OL - k k k frequeny in hertz Figure 4: the put ipedane is low in d but rises with frequeny as an indutive eleent would do. Deriving an approxiate put ipedane definition In the above lines, we have used the ter alost to opare the open and losed-loop put ipedanes at the ross over frequeny. However, let us try to see how lose they are in the viinity of the ross over point. To alulate the odule of the Eq. (5) right ter,,there are several ethods. One of the + T( s) onsists in applying a sinusoidal odulation to the oplete hain ade of the onverter transfer funtion H(s) followed by the opensator transfer funtion G(s). This is exatly what we would do in the laboratory to explore the true open loop response of our opensated onverter. However, in this partiular ase, rather than expressing the odulation signal via a lassial for A ˆ sin ( ωt+ ϕ ), we will use a phasor notation where ϕ represents the phase lag brought by the total hain when stiulated at the ross over frequeny. This is what Figure 5 details where a -V odulation is assued. jω ~ T(s) V ( ω ) j T j e ϕ ϕ = arg T T(s) ( j ω ) Figure 5: a sinusoidal signal an also be represented by a rotating vetor expressed using the Euler notation. The phasor notation an be updated using Euler s forula as Eq. (8) shows: jϕ ( ) = ( ) = ( ) os( ϕ ) + sin ( ϕ ) T s T s e T s j (8) In this equation, the ter ϕ relates to the phase differene between the put signal and the input odulation. A design riteria for us is not ϕ but ϕ, our phase argin. To help linking both ters together, Figure 6 shows the ontribution of the loop to the total phase lag.

5 f arg T ( f ) -8 ϕ Figure 6: the phase argin is the distane between ϕ and the 8 axis. Based on the figure, we an write: Solving for ϕ, we have: Based on the above equation, we an update Eq. (8): ( ) 8 = argt jω ϕ (9) ( j ) ϕ = argt ω = ϕ 8 () jϕ ( ω ) = ( ω ) os( ϕ 8) + sin ( ϕ 8) = ( ω ) os( ϕ ) sin ( ϕ ) T j e T j j T j j () Knowing that the loop gain odule at ross over is, then T(s) an be approxiated to be: ( ) os( ϕ ) jsin ( ϕ ) T s Based on this result, we an now update Eq. (5) as follows: = (), CL ( s) =, OL ( s) =, OL ( s) + T( s) os ϕ ϕ ( ) j sin ( ) (3) Solving this equation leads to:, CL ( s) π fc os ( ϕ ) (4) As we an see, the odule of the apaitor ipedane is now affeted by a ter dependent upon the phase argin. We an now plot the variations of this ter versus the phase argin as proposed by Figure 7.

6 + T f ( ) φ 36 π Figure 7: the phase argin degrades the put ipedane below 6. As observed, a phase argin below 6 degrades the put ipedane of the onverter and it slightly iproves it above. A design exaple Let us assue we have a power supply where the put apaitor is µf. This hoie has been ade by the designer onsidering the voltage put ripple onditions and the orresponding rs urrent irulating in the apaitor. The speifiation asks us a axiu voltage drop of 8 V when the onverter undergoes a urrent step I of A. What bandwidth do we need to reah this paraeter? If we use Eq. (3) and apply a -A step, we an predit the voltage drop by: Fro this equation, it is easy to extrat the iniu ross over point: I V (5) π f C f I = = 4 khz V C π 8 π (6) Based on this result, we ust hek that the apaitor ESR is lower than: = = 4Ω π 4k (7) We found that a -µf apaitor fro the Panasoni FM series ould be the right hoie. Fro the anufaturer data-sheet, the oponent features an ESR of 9 Ω at khz. This ESR alone will ontribute to a drop of 9 = 38 V whih is 47% of our speifiation. To offer soe argin in our design, we will inrease the ross over frequeny to 6 khz and purposely opensate our onverter to eet this goal. One opensated, our 5-V voltage-ode buk onverter loop gain Bode plot SPICE siulation appears in Figure 8. It shows a ross over frequeny of 5.8 khz together with a rather ofortable phase argin of 76. The put voltage drop is now going to split between the apaitor and its ESR ter. Based on a 76 phase argin, we an approxiate the apaitive ontribution by using Eq. (4): V, C = = 44.5 V (8) k os 76 ( )

7 6. 8 T(s) arg T(s) Plot vdberr in db(volts) ph_verr in degrees PM=76 f = 5.8 khz k k k frequeny in hertz Figure 8: the opensation leads to a ross over frequeny of 5.8 khz with a phase argin of 78. We are now going to step load the put by a urrent soure ranging fro A to. A in a -µs tie frae. The siulation results are shown in Figure 9. We an see that the total put undershoot is well within our design goals with a theoretial 53.5-V deviation. The ESR spike is 35 V and lasts only during the put urrent irulation in the apaitor. The apaitive ontribution reahes 5 V, in a fairly good agreeent with Eq. (4) preditions. 5. Plot v in volts V 4.94 V Plot3 v in volts V V C 3. Plot vesr in volts V V ESR tie in seonds Figure 9: the -A step load gives an undershoot well under ontrol. As an be seen, the ESR ter aplitude depends on the urrent step undergone by the put. When the load hange is slow enough, the loop has a eans to attenuate the ESR ontribution. However, ost of the tie, the transient loading onditions are so fast that all the urrent step translates into a voltage spike over the ESR. Given its steepness, the loop annot fight it. The situation degrades further if the put urrent rate of hange reahes high values, like in otherboard appliations for instane. In that ase, the indutive ter alled the

8 Equivalent Series Indutane (ESL) of the apaitor starts to enter the piture and the situation worsens. In these extree ases, the apaitor seletion is alost solely based on the ontribution of its parasiti ters and no longer on its apaitive value. Conlusion This artile has shown the link between the ross over frequeny and the onverter undershoot in response to a load step. The designer an now analytially selet a ross over frequeny rather than arbitrarilly hosing it based on the swithing. If the apaitor ipedane plays a role in relationship with the seleted ross over frequeny, there are other ters whose ontribution is of ontrol. These are the ESR and the Equivalent Series Indutor (ESL) of the put apaitor. They are respetively sensitive to the put urrent step and the urrent slope. As loop ontrol has alost no influene on their ontributions, it is the designer task to ake sure these parasiti ters stay low enough to keep the overall transient response within the original speifiations. Referenes. C. Basso, Swith Mode Power Supplies: SPICE Siulations and Pratial Designs, MGraw-Hill, 8