A Heuristic Method for Statistical Digital Circuit Sizing

A Heuristic Method for Statistical Digital Circuit Sizing Stephen Boyd Seung-Jean Kim Dinesh Patil Mark Horowitz Microlithography 06 2/23/06

Statistical variation in digital circuits growing in importance as devices shrink modeling still open many sources: environmental, process parameter variation, lithography intrachip, interchip variation distributions, correlations not well known, change as process matures Microlithography 06 2/23/06 1

Statistical digital circuit sizing standard design approaches: margining, guardbanding, design over corners statistical design explicitly takes statistical variation into account (combines circuit design with design for manufacturing, yield optimization, design centering,... ) statistical design is very hard problem (even for small circuits) this talk: a (relatively) simple heuristic method for statistical design that appears to work well Microlithography 06 2/23/06 2

Outline A quick example Digital circuit sizing: models and optimization New method for statistical digital circuit sizing Digital circuit sizing example Conclusions and future work Microlithography 06 2/23/06 3

A Quick Example

Example: Ladner-Fisher 32-bit adder 64 inputs, 33 outputs, 451 gates, 3214 paths, max depth 8 simplified RC delay model design variables: 451 scale factors for gates cycle time T cycle is max path delay minimize cycle time subject to limits on area, min/max scale factor Microlithography 06 2/23/06 4

Optimization results (no statistical variation) path delays with optimized & uniform scale factors (same total area) PSfrag replacements 4000 # of paths 2000 optimal uniform 0 0 20 40 60 80 100 path delay Microlithography 06 2/23/06 5

Statistical variation in gate delay PSfrag replacements simple Pelgrom model; larger gates have less (relative) variation in delay min sized gate has 10% variation x = 5 probability x = 2 x = 1 1 2 3 4 5 6 7 delay Microlithography 06 2/23/06 6

Effects of statistical variation on nominal optimal design T cycle PDF estimated via Monte Carlo PSfrag replacements nominal T cycle Q.95 (T cycle ) cycle time PDF 45 47 49 51 53 55 cycle time Microlithography 06 2/23/06 7

Why isn t T cycle PDF centered around nominal value? T cycle is max of 3214 random path delays max of RVs behaves differently from sum of RVs in sum, negative and positive deviations tend to cancel out; PDF is centered, has smaller relative variation in max, large deviation of any leads to large value; PDF is shifted, skewed to right, has large relative deviation Microlithography 06 2/23/06 8

PSfrag replacements PDF of sum of random variables Z = M i=1 X i, X i N (1, 0.1) independent PDF M = 1 0.5 1 1.5 PDF M = 10 5 10 15 PDF M = 100 50 100 150 Microlithography 06 2/23/06 9

PSfrag replacements PDF of max of random variables Z = max{x 1,..., X M }, X i N (1, 0.1) independent PDF M = 1 PDF M = 10 PDF M = 100 0.5 1 1.5 Microlithography 06 2/23/06 10

Simple worst-case design use slow model for all gates, e.g., 1.2D i gives same design can we do better? Microlithography 06 2/23/06 11

Statistically robust design via new method same circuit, uncertainty model, and constraints PSfrag replacements distribution of cycle time robust design nominal optimal design 46 47 48 49 50 51 52 53 cycle time Microlithography 06 2/23/06 12

Statistically robust design via new method nominal delay E D σ D Q.95 (D) nominal optimal 45.9 49.4 0.91 51.1 robust 46.5 47.6 0.29 48.1 same circuit, uncertainty model, and constraints compared to nominal optimal design, some gates are upsized, others are downsized Microlithography 06 2/23/06 13

Nominal vs. statistical robust designs 4000 PSfrag replacements # of paths 2000 0 0 20 40 60 path delay Microlithography 06 2/23/06 14

Path delay mean/std. dev. scatter plots path delay std. dev. path delay std. dev. PSfrag replacements 3 0 10 3 0 10 nominal optimal design mean path delay robust design mean path delay 50 50 Microlithography 06 2/23/06 15

Area/delay trade-off analysis 15000 PSfrag replacements 11000 A max 7000 robust design nominal optimal design 3000 45 55 65 nominal cycle time Microlithography 06 2/23/06 16

Area/delay trade-off analysis 15000 PSfrag replacements 11000 A max 7000 robust design nominal optimal design 3000 45 55 65 95% cycle time Microlithography 06 2/23/06 17

Digital Circuit Sizing: Models

R A R B R C input flip flops 1 Gate scaling combinational logic block output flip flops 4 6 in 2 out C X C Y 3 5 7 clock combinational logic; circuit topology & gate types given gate sizes (scale factors x i 1) to be determined scale factors affect total circuit area, power and delay Microlithography 06 2/23/06 18

PSfrag replacements R i RC gate delay model V dd C in i C in i R i C int i C L i input & intrinsic capacitances, driving resistance, load capacitance C in i = C in i x i, C int i = C int i x i, R i = R i /x i, C L i = C in j j FO(i) RC gate delay: D i = 0.69R i (C L i + C int i ) Microlithography 06 2/23/06 19

Path and circuit delay 1 PSfrag replacements 4 6 2 5 7 3 delay of a path: sum of delays of gates on path circuit delay (cycle time): maximum delay over all paths Microlithography 06 2/23/06 20

Area & power total circuit area: A = x 1 Ā 1 + + x n Ā n total power is P = P dyn + P stat n dynamic power P dyn = f i (Ci L i=1 f i is gate switching frequency static (leakage) power P stat = I leak i n i=1 + C int i )V 2 dd Ii leak V dd is leakage current (average over input states) Microlithography 06 2/23/06 21

Parameters used in example model parameters: gate type Cin Cint R Ā INV 3 3 0.48 3 NAND2 4 6 0.48 8 NOR2 5 6 0.48 10 AOI21 6 7 0.48 17 OAI21 6 7 0.48 16 time unit is τ, delay of min-size inverter (0.69 0.48 3 = 1) area (total width) unit is width of NMOS in min-size inverter Microlithography 06 2/23/06 22

Statistical variation in threshold voltage we focus on statistical variation in threshold voltage V th (can also model variations in other parameters, e.g., t ox, L eff,... ) Pelgrom model: σ Vth = σ Vth x 1/2 where σ 2 V th is V th variance for unit scaled gate larger gates have less V th variation Microlithography 06 2/23/06 23

alpha-power law model: Statistical gate delay model D V dd (V dd V th ) α (α 1.3) for small variation in V th, σ D D σ V th = α(v dd V th ) 1 σ Vth x 0.5 D V th gate scaling affects mean delay and relative variation differently relative variation decreases as gate scale factor increases: σ D /D x 0.5 Microlithography 06 2/23/06 24

Statistical variation in gate delay PSfrag replacements 10% relative variation for min sized gate (σ D /D = 0.1) inverter driving C L = 4 x = 5 probability x = 2 x = 1 1 2 3 4 5 6 7 delay Microlithography 06 2/23/06 25

inverter driving C L = 4 PSfrag replacements Statistical variation in gate delay 10τ µ + 3σ delay 5τ µ µ 3σ 0 1 2 3 4 5 scale factor Microlithography 06 2/23/06 26

Statistical leakage power model leakage current (V 0 0.04) I leak xe V th/v 0 linearization does not give accurate prediction of E I leak, σ I leak exact values for V th Gaussian: E I leak = I leak,nom e σ2 V th /(2V 2 0 x), σ I leak = (e σ2 V th /(V 2 0 x) 1) 1/2 E I leak I leak,nom is leakage current when statistical variation is ignored Microlithography 06 2/23/06 27

Effects of statistical variation on leakage power V th N ( V th, 0.15 V th ), V th = 0.25, V 0 = 0.04 x = 1 PSfrag replacements PDF x = 2 x = 5 I leak xe V th /V 0 Microlithography 06 2/23/06 28

Statistical variation in leakage power 1.7 PSfrag replacements E I leak /I leak,nom 1 1 2 3 4 5 scale factor Microlithography 06 2/23/06 29

Digital Circuit Sizing: Optimization

Basic gate scaling problem (no statistical variation) minimize D subject to P P max, A A max 1 x i, i = 1,..., n a geometric program (GP); can be solved efficiently extensions/variations: minimize area, power, or some combination maximize clock frequency subject to area, power limits add other constraints optimal trade-off of area, power, delay Microlithography 06 2/23/06 30

Statistical parameter variation now model gate delay & power as random variables circuit performance measures P, D become random variables P, D distributions of P, D depend on gate scalings x i for fixed design, can estimate PDFs of P, D via Monte Carlo PSfrag replacements frequency 45 53 cycle time D Microlithography 06 2/23/06 31

Statistical design measure random performance measures by 95% quantile (say) minimize Q.95 (D) subject to Q.95 (P) P max, A A max 1 x i, i = 1,..., n extremely difficult stochastic optimization problem; almost no analytic/exact results but, simple heuristic method works well Microlithography 06 2/23/06 32

The New Method

Statistical power constraint total power is sum of gate powers E P = n E P i i=1 if n is large and P 1,..., P m are independent (enough), P n E P i i=1 can use E P P max as reasonable approximation of Q.95 (P) P max Microlithography 06 2/23/06 33

define surrogate gate delays Surrogate gate delay PSfrag replacements D i (x) = D i (x) + κ i σ i (x) κ i σ i (x) is margin on gate delay (κ i is typically 2) µ + κσ gate delay µ gives more margin to smaller gates scale factor Microlithography 06 2/23/06 34

Interpretation of gate delay margins margins κ i σ i (x) take statistical gate delay variation into account κ i related to Prob (D i µ i + κ i σ i ) Chebyshev inequality: Prob (D i µ i + κ i σ i ) κ2 i 1 + κ 2 i if D i is Gaussian Prob (D i µ i + κ i σ i ) = 1 2π κ i e t 2 /2 dt Microlithography 06 2/23/06 35

Heuristic for statistical design use modified (leakage) power model taking into account statistical variation use surrogate gate delays D i (x) = D i (x) + κ i σ i (x) now solve resulting (deterministic) gate scaling problem verify statistical performance via Monte Carlo analysis (can update κ i s and repeat) Microlithography 06 2/23/06 36

Digital Circuit Sizing Example

Statistically robust design via new method same circuit, uncertainty model, and constraints PSfrag replacements distribution of cycle time robust design nominal optimal design 46 47 48 49 50 51 52 53 cycle time Microlithography 06 2/23/06 37

Path delay mean/std. dev. scatter plots path delay std. dev. path delay std. dev. PSfrag replacements 3 0 10 3 0 10 nominal optimal design mean path delay robust design mean path delay 50 50 Microlithography 06 2/23/06 38

PSfrag replacements Comparison of nominal optimal and robust designs # of gates 400 nominal optimal design 0 1 2 4 8 16 32 400 # of gates robust design 0 1 2 4 8 scale factor 16 32 Microlithography 06 2/23/06 39

Comparison of nominal optimal and robust designs PSfrag replacements 32 scale factor (robust design) 16 8 4 2 1 1 2 4 8 16 32 scale factor (nominal optimal design) Microlithography 06 2/23/06 40

Effect of margin coefficients 52 PSfrag replacements 95% cycle time 50 48 46 0 1 2 3 4 5 κ Microlithography 06 2/23/06 41

Sensitivity to model assumptions question: how sensitive is robust design to our model of process variation? distribution shape correlation between gates Pelgrom model of variance vs. scale factor answer: not very Microlithography 06 2/23/06 42

PSfrag replacements Simulation with uniform gate delay distributions distribution of cycle time robust design nominal optimal design 46 47 48 49 50 51 52 53 cycle time compared with Gaussian gate delays: nominal optimal design not quite as bad; robust design still quite good Microlithography 06 2/23/06 43

PSfrag replacements Simulation with correlated gate delays connected gates have delays that are 30% correlated robust design distribution of cycle time nominal optimal design 46 47 48 49 50 51 52 53 cycle time nominal optimal not as bad; but robust design still quite good Microlithography 06 2/23/06 44

Conclusions and Future Work

Conclusions statistically robust design is subtle; cannot be done by hand exact or direct methods will not work well computationally intractable depend on details of statistical models heuristic method is relatively simple, scales well, gives good designs reduces problem to a deterministic one Microlithography 06 2/23/06 45

References Boyd, Kim, and Mohan, DATE Tutorial 2005 Geometric programming and its applications to EDA problems Boyd, Kim, Patil, and Horowitz, SPIE ML 2006 A heuristic method for statistical digital circuit sizing Kim, Boyd, Patil, and Horowitz, Optimization and Engineering, 2006 A heuristic for optimizing stochastic activity networks with applications to statistical digital circuit sizing Boyd, Kim, Patil, and Horowitz, Operations Research, 2005 Digital circuit optimization via geometric programming Patil, Yun, Kim, Cheung, Horowitz, and Boyd, ISQED 2005 A new method for design of robust digital circuits all available from www.stanford.edu/ boyd/research.html Microlithography 06 2/23/06 46

References (continued) Mani, Devgan, Orshansky, DAC 2005 An efficient algorithm for statistical minimization of total power under timing yield constraints Satish, Ravindran, Moskewicz, Chinnery, and Keutzer, UCB tech. report, 2005 Evaluating the effectiveness of statistical gate sizing for power optimization Bhardwaj and Vrudhula, DAC 2005 Leakage minimization of nano-scale circuits in the presence of systematic and random variations Microlithography 06 2/23/06 47