MiCOM P443-6/P543-7/P841 Release Notes P443-6/P543-7/P841 Upgrade Platform Hardware Version: M, P Platform Software Version: 75, 65, 45 Publication Reference: P443-6/P543-7/P841-RNC1-TM-EN-1 ALSTOM 2013. All rights reserved. Information contained in this document is indicative only. No representation or warranty is given or should be relied on that it is complete or correct or will apply to any particular project. This will depend on the technical and commercial circumstances. It is provided without liability and is subject to change without notice. Reproduction, use or disclosure to third parties, without express written authority, is strictly prohibited.
Contents Supplement 1 P443-6/P543-7/P841 Release Notes 1 1 Introduction 3 2 Second Harmonic Blocking Using SEF Input 4 2.1 Second Harmonic Blocking Using SEF Protection DDBs 4 2.2 Second Harmonic Blocking Using SEF Input Settings 4 2.3 Second Harmonic Blocking Using SEF Input Logic 4 3 Display Check Sync Difference Voltage 6 4 Hot-Standby Ethernet Failover 7 4.1 Hot-Standby Ethernet Failover Settings 7 5 Loss of SNTP Server Signal Alarm 8 6 Circuit Breaker Fail Logic 9 7 CB Fail DDB signals 15
Contents P443-6/P543-7/P841 ii P443-6/P543-7/P841-RNC1-TM-EN-1
P443-6/P543-7/P841 RELEASE NOTES SUPPLEMENT 1
Supplement 1 - P443-6/P543-7/P841 Release Notes P443-6/P543-7/P841 2 P443-6/P543-7/P841-RNC1-TM-EN-1
P443-6/P543-7/P841 Supplement 1 - P443-6/P543-7/P841 Release Notes 1 INTRODUCTION These release notes apply to the following products: P443 P445 P446 P543 P544 P545 P546 P547 P841A P841B P443-6/P543-7/P841-RNC1-TM-EN-1 3
Supplement 1 - P443-6/P543-7/P841 Release Notes P443-6/P543-7/P841 2 SECOND HARMONIC BLOCKING USING SEF INPUT Second harmonics can cause unwanted tripping, for example in inrush waveforms. This function calculates the second harmonic current using the SEF CT input and compares it with the ISEF>2nd Harm threshold setting. The minimum detection level is 4 ma rms. The maximum detection level is 1.8 A rms in any sample over the previous cycle. There is no delay on pick-up but there is a 1 cycle delay on drop-off. 2.1 SECOND HARMONIC BLOCKING USING SEF PROTECTION DDBS Ordinal Signal Name Source Type Response Description 1723 lh(2) Blk SEF Software PSL Input Protection Event Second harmonic detected in SEF input 2.2 SECOND HARMONIC BLOCKING USING SEF INPUT SETTINGS Menu Text Col Row Default Setting Available Setting Description ISEF HARM. BLOCK 46 20 This column contains settings for SEF input 2nd harmonic blocking ISEF>2nd Detect. 46 21 Disabled 0 = Disabled or 1 = Enabled This setting enables or disables SEF Input 2nd Harmonic Blocking ISEF>2nd Harm. 46 22 20 10 to 100 step 1 This sets the percentage of second harmonic current in the primary at which blocking occurs. 2.3 SECOND HARMONIC BLOCKING USING SEF INPUT LOGIC Second harmonic components can be detected using the standard phase CT inputs. For low magnitudes of secondary current, the SEF input can be used. When second harmonics are detected, the PSL can be used to block protection. This is done using the timer block DDB signals. For secondary currents above 1.8 A rms, the SEF CT starts to saturate. The second harmonic content is then not a true representation. In this case, phase CT detection can be used with the SEF CT to cover the full range of secondary current. The following diagram shows how this can be done in PSL. The table shows the allocation of signal names to DDBs. In this example the ISEF>3 protection is blocked. Map DDB Ih(2) Blk SEF to ISEF>1 Timer Blk, ISEF>2 Timer Blk, ISEF>3 Timer Blk and ISEF>4 Timer Blk. 4 P443-6/P543-7/P841-RNC1-TM-EN-1
P443-6/P543-7/P841 Supplement 1 - P443-6/P543-7/P841 Release Notes Ih(2) Blk SEF Ih(2) Loc Blk A Ih(2) Loc Blk B 1 ISEF>3 Timer Blk Ih(2) Loc Blk C Ih(2) Loc Blk N E02045 Figure 1: Second harmonic blocking of SEF using PSL Signal Name DDB # ISEF>3 Timer Blk 411 Ih(2) Blk SEF 1723 Ih(2) Loc Blk A 1016 Ih(2) Loc Blk B 1017 Ih(2) Loc Blk C 1018 Ih(2) Loc Blk N 1019 P443-6/P543-7/P841-RNC1-TM-EN-1 5
Supplement 1 - P443-6/P543-7/P841 Release Notes P443-6/P543-7/P841 3 DISPLAY CHECK SYNC DIFFERENCE VOLTAGE This function monitors the difference between the bus and line values of frequency, angle and voltage magnitude. The CB is usually closed automatically. If it is closed manually, you need these measurements to be able to decide when to close it. This function supports Courier, CS103 Generic Services, DNP3 and IEC 61850 protocols. The IEC 61850 Logical Node Asc RSYN is used to display the measurement. For single breaker IEDs, C/S Bus-Line Mag cell is visible if System Checks is set to Enabled. For dual breaker IEDs, the CB1 Bus-Line Mag and CB2 Bus-Line Mag cells are visible if System Checks is set to Enabled. 6 P443-6/P543-7/P841-RNC1-TM-EN-1
P443-6/P543-7/P841 Supplement 1 - P443-6/P543-7/P841 Release Notes 4 HOT-STANDBY ETHERNET FAILOVER This is used for products which do not have Ethernet redundancy and applies only to those using single Ethernet boards. This board has one fibre and one copper interface. If there is a fault on the fibre channel it can switch to the copper channel, or vice versa. Px4x products which use the Parallel Redundancy Protocol (PRP) do not need this function. When this function detects a link failure, it generates the NIC Fail Alarm. The failover timer then starts, which has a settable timeout of 2 to 60 secs in 100 ms steps. During this time, the Hot Standby Failover function continues to check the status of the other channel. If the link failure recovers before the failover timer times out, the channels are not swapped over. If there is still a fail when the failover timer times out and the other channel status is ok, the channels are swapped over. The Ethernet controller is then reconfigured and the link is renegotiated. 4.1 HOT-STANDBY ETHERNET FAILOVER SETTINGS To set the function: 1. Start S1 Agile. 2. Click the Ethernet Configuration tile. 3. Start the IEC 61850 IED Configurator. Working offline: 1. Click the icon New MiCOM Configuration from an Installed ICD File. 2. Double-click the product variant. 3. Double-click the Communications item. Or working online: 1. Select Device > Manage IED. 2. Select the IED type device number. 3. Select the IED address and click Next. The IED 61850 Configurator tool reads information from the IED and shows them in the Summary view. 4. Click the Communications tab to read and edit the settings. Then: 1. The Media setting defines the default interface used to communicate between clients and peers, and the MiCOM IED. The value is taken from the ConnectedAP/PhysConn section of the configured SCL file and is editable in Manual Editing Mode. The single Ethernet board has one fibre and one copper interface. If you are using fibre, select Single Fibre. If you are using copper, select Single Copper or Redundant Fibre. If you are using a Redundant Ethernet board, select Single Copper or Redundant Fibre. 2. Set the Ethernet Failover to Enable and adjust the Failover Timeout as required. This does not appear if the product does not have Ethernet Failover. P443-6/P543-7/P841-RNC1-TM-EN-1 7
Supplement 1 - P443-6/P543-7/P841 Release Notes P443-6/P543-7/P841 5 LOSS OF SNTP SERVER SIGNAL ALARM This function issues an alarm when there is a loss of time synchronization on the SNTP server. It is issued when the SNTP sever has not detected a valid time synchronisation response within its 5 second window. This is because there is no response or no valid clock. The alarm is mapped to IEC 61850. 8 P443-6/P543-7/P841-RNC1-TM-EN-1
P443-6/P543-7/P841 Supplement 1 - P443-6/P543-7/P841 Release Notes 6 CIRCUIT BREAKER FAIL LOGIC The CB Fail logic diagrams are the same for CB1 and CB2. Signal names are shown using CB(n) where n represents single or dual breaker, depending on the product. ExtTrip Only Init Enable Current Prot SEF Trip ISEF < Start TripStateSEF SEFCBFTimer_AND_ZCD_SEF WI Prot Reset Enable Aid1 WI Trip 3Ph Aid2 WI Trip 3Ph Aid 1 WI Trip A Aid 2 WI Trip A WI INFEED A WI INFEED A WI INFEED B Aid 1 WI Trip B Aid 2 WI Trip B Aid 1 WI Trip C Aid 2 WI Trip C WI INFEED B WI INFEED C WI INFEED C CB(n) External Trip A TripStateExt A CB(n) 4 Pole Dead A 3 CB(n) Ext Trip Reset 0 I < Only 1 CB Open & I< 2 Prot Reset & I< 3 Prot Reset OR I<1 4 Prot Reset OR (CB Open & I< ) CB(n) IA<Start CBFTimerA_AND_ZCD_A 4 Latch ATrip Reset Incomp 3 0 0 Key: External DDB Signal Hidden DDB Signal Setting cell Setting value E00658 Note on SR Latches All latches are reset dominant and are triggered on the positive edge. If the edge occurs while the reset is active, the detection of the edge is delayed until the reset becomes non-active. AND gate & OR gate 1 SR Latch S Q R Timer Figure 2: Circuit Breaker Fail Logic - part 1 P443-6/P543-7/P841-RNC1-TM-EN-1 9
Supplement 1 - P443-6/P543-7/P841 Release Notes P443-6/P543-7/P841 CB(n) Ext Trip B TripStateExt B CB(n) 4 Pole Dead B CB(n) IB<Start CBFTimerB_AND_ZCD_B 3 CB(n) Ext Trip Reset 0 I < Only 1 CB Open & I< 2 Prot Reset & I< 3 Prot Reset OR I<1 4 Prot Reset OR (CB Open & I< ) 4 Latch BTrip Reset Incomp 3 0 CB(n) Ext Trip C TripStateExt C CB(n) 4 Pole Dead C 3 CB(n) Ext Trip Reset 0 I < Only 1 CB Open & I< 2 Prot Reset & I< 3 Prot Reset OR I<1 4 Prot Reset OR (CB Open & I< ) CB(n) IC<Start CBFTimerC_AND_ZCD_C 4 Latch CTrip Reset Incomp 3 E00659 0 Note on SR Latches All latches are reset dominant and are triggered on the positive edge. If the edge occurs while the reset is active, the detection of the edge is delayed until the reset becomes non-active. Key: External DDB Signal Hidden DDB Signal Setting cell Setting value AND gate & OR gate 1 SR Latch S Q R Timer Figure 3: Circuit Breaker Fail Logic - part 2 10 P443-6/P543-7/P841-RNC1-TM-EN-1
P443-6/P543-7/P841 Supplement 1 - P443-6/P543-7/P841 Release Notes TripStateExt A CB(n) TripStateA WI INFEED A TripStateExt B CB(n) TripStateB WI INFEED B TripStateExt C CB(n) TripStateC WI INFEED C ExtTrip Only Init Enable Any Trip Phase A CB(n) CB(n) IA<Start CBFTimerA_AND_ZCD_ZA ExtTrip Only Init Enable Any Trip Phase B CB(n) CB(n) IB<Start CBFTimerB_AND_ZCD_ZB ExtTrip Only Init Enable Any Trip Phase C CB(n) CB(n) IC<Start CBFTimerC_AND_ZCD_ZC S Key: External DDB Signal Note on SR Latches All latches are reset dominant and are triggered on the positive edge. If the edge occurs while the reset is active, the detection of the edge is delayed until the reset becomes non-active. Hidden DDB Signal Setting cell Setting value AND gate & OR gate 1 E00660 SR Latch S Q R Timer Figure 4: Circuit Breaker Fail Logic - part 3 P443-6/P543-7/P841-RNC1-TM-EN-1 11
Supplement 1 - P443-6/P543-7/P841 Release Notes P443-6/P543-7/P841 CB(n) Ext Trip3ph 4 CB(n) IA<Start CB(n) IB<Start CB(n) IC<Start 3 CB(n) Ext Trip Reset 0 I < Only 1 CB Open & I< 2 Prot Reset & I< 3 Prot Reset OR I<1 4 Prot Reset OR (CB Open & I< ) CB(n) ZCD State A CB(n) ZCD State B CB(n) ZCD State C CBFTimerA_AND_ZCD_A CBFTimerB_AND_ZCD_B CBFTimerC_AND_ZCD_C All Poles Dead Pole Dead A Pole Dead B Pole Dead C 4 3 Latch 3phTrip Reset Incomp S ExtTrip Only Init Enable 0 CBF Non I Trip CB(n) IA<Start CB(n) IB<Start CB(n) IC<Start CB(n) ZCD State A CB(n) Non_I_Reset 0 I < Only 1 CB Open & I< 2 Prot Reset & I< CB(n) ZCD State B CB(n) ZCD State C CBFTimerA_AND_ZCD_A CBFTimerB_AND_ZCD_B Latch NonITrip Reset Incomp CBFTimerC_AND_ZCD_C All Poles Dead Pole Dead A Pole Dead B Pole Dead C Note on SR Latches All latches are reset dominant and are triggered on the positive edge. If the edge occurs while the reset is active, the detection of the edge is delayed until the reset becomes non-active. 0 Key: External DDB Signal Hidden DDB Signal Setting cell Setting value AND gate & OR gate 1 E00661 SR Latch S Q R Timer Figure 5: Circuit Breaker Fail Logic - part 4 12 P443-6/P543-7/P841-RNC1-TM-EN-1
Latch_ATrip_Reset_Incomp Latch_BTrip_Reset_Incomp Latch_CTrip_Reset_Incomp Latch_3phTrip_Reset_Incomp Latch_NonITrip_Reset_Incomp CB(n) Fail 1 Status Enable Disable CB(n) Fail 2 Status Enable Disable CB(n) ZCD State A WI INFEED A TripStateA CB(n) ZCD State B WI INFEED B TripStateB E00662 Key: External DDB Signal Hidden DDB Signal Setting cell Setting value AND gate & OR gate 1 SR Latch Q Timer S R CB(n) Fail 1 Timer 0 CB(n) Fail 2 Timer 0 CB(n) Fail 1 Timer 0 CB(n) Fail 2 Timer 0 T U V W X Y Z CB(n) Fail1 Trip CB Fail Alarm CB(n) Fail2 Trip CB(n) Fail1 Trip A CBFTimerA_AND_ZCD_A CB(n) Fail2 Trip A CB(n) Fail1 Trip B CBFTimerB_AND_ZCD_B CB(n) Fail2 Trip B t t t t P443-6/P543-7/P841 Supplement 1 - P443-6/P543-7/P841 Release Notes Figure 6: Circuit Breaker Fail Logic - part 5 P443-6/P543-7/P841-RNC1-TM-EN-1 13
T U V W X Y Z CB(n) ZCD State C WI INFEED C TripStateC CB(n) Fail1 Trip C 0 CB(n) Fail 1 Timer CBFTimerC_AND_ZCD_C 0 CB(n) Fail2 Trip C CB(n) Fail 2 Timer ZCDStateSEF TripStateSEF 0 CB(n) Fail 1 Timer SEFCBFTimer_AND_ZCD_SEF 0 CB(n) Fail 2 Timer Key: External DDB Signal Hidden DDB Signal Setting cell Setting value AND gate & OR gate 1 E00663 SR Latch Q Timer S R t t t t Supplement 1 - P443-6/P543-7/P841 Release Notes P443-6/P543-7/P841 Figure 7: Circuit Breaker Fail Logic - part 6 CBF elements CB Fail 1 Timer and CB Fail 2 Timer can be configured to operate for trips triggered by protection elements within the device or via an external protection trip. The latter is achieved by allocating one of the opto-isolated inputs to "External Trip" using the programmable scheme logic. It is possible to reset the CBF from a breaker open indication (from the Pole Dead logic) or from a protection reset. In these cases resetting is only allowed if the undercurrent elements have also been reset. 14 P443-6/P543-7/P841-RNC1-TM-EN-1
P443-6/P543-7/P841 Supplement 1 - P443-6/P543-7/P841 Release Notes 7 CB FAIL DDB SIGNALS Ordinal English Text Source Type Response Function Description 298 CB Fail Alarm CB Fail PSL Input Latched Alarm Event Circuit breaker fail alarm 298 CB1 Fail Alarm CB Fail PSL Input Latched Alarm Event Circuit breaker 1 fail alarm 534 External Trip3ph PSL PSL Output No Response External trip 3 phase - allows external protection to initiate breaker fail, circuit breaker condition monitoring statistics, and internal auto-reclose (if enabled) 534 CB1 Ext Trip3ph PSL PSL Output No Response CB1 Ext Trip3ph - allows external protection to initiate breaker fail, circuit breaker condition monitoring statistics, and internal auto-reclose (if enabled) of CB1 535 External Trip A PSL PSL Output No Response External trip A phase - allows external protection to initiate breaker fail, circuit breaker condition monitoring statistics, and internal auto-reclose (if enabled) 535 CB1 Ext Trip A PSL PSL Output No Response CB1 Ext Trip A - allows external protection to initiate breaker fail, circuit breaker condition monitoring statistics, and internal auto-reclose (if enabled) (A Ph) of CB1 536 External Trip B PSL PSL Output No Response External trip B phase - allows external protection to initiate breaker fail, circuit breaker condition monitoring statistics, and internal auto-reclose (if enabled) 536 CB1 Ext Trip B PSL PSL Output No Response CB1 Ext Trip B - allows external protection to initiate breaker fail, circuit breaker condition monitoring statistics, and internal auto-reclose (if enabled) (B Ph) of CB1 537 External Trip C PSL PSL Output No Response External trip C phase - allows external protection to initiate breaker fail, circuit breaker condition monitoring statistics, and internal auto-reclose (if enabled) 537 CB1 Ext Trip C PSL PSL Output No Response CB1 Ext Trip C - allows external protection to initiate breaker fail, circuit breaker condition monitoring statistics, and internal auto-reclose (if enabled) (C Ph) of CB1 538 CB2 Ext Trip3ph PSL PSL Output No Response CB2 Ext Trip3ph - allows external protection to initiate breaker fail, circuit breaker condition monitoring statistics, and internal auto-reclose (if enabled) of CB2 539 CB2 Ext Trip A PSL PSL Output No Response CB2 Ext Trip A - allows external protection to initiate breaker fail, circuit breaker condition monitoring statistics, and internal auto-reclose (if enabled) (A Ph) of CB2 540 CB2 Ext Trip B PSL PSL Output No Response CB2 Ext Trip B - allows external protection to initiate breaker fail, circuit breaker condition monitoring statistics, and internal auto-reclose (if enabled) (B Ph) of CB2 541 CB2 Ext Trip C PSL PSL Output No Response CB2 Ext Trip C - allows external protection to initiate breaker fail, circuit breaker condition monitoring statistics, and internal auto-reclose (if enabled) (C Ph) of CB2 642 Aid1 WI Trip 3Ph Aided Scheme Logic PSL Input Protection Event Aided scheme 1 Weak Infeed logic trip 3 phase 647 Aid 2 WI Trip A Aided Scheme Logic PSL Input Protection Event P443-6/P543-7/P841-RNC1-TM-EN-1 15
Supplement 1 - P443-6/P543-7/P841 Release Notes P443-6/P543-7/P841 Ordinal English Text Source Type Response Function Description Aided scheme 2 Weak Infeed trip phase A 648 Aid 2 WI Trip B Aided Scheme Logic PSL Input Protection Event Aided scheme 2 Weak Infeed trip phase B 649 Aid 2 WI Trip C Aided Scheme Logic PSL Input Protection Event Aided scheme 2 Weak Infeed trip phase C 652 Aid2 WI Trip 3Ph Aided Scheme Logic PSL Input Protection Event Aided scheme 2 Weak Infeed logic trip 3 phase 834 Bfail1 Trip 3ph CB Fail PSL Input Protection Event Three phase output from circuit breaker failure logic, stage 1 834 CB1 Fail1 Trip CB Fail PSL Input Protection Event Three phase output from circuit breaker 1 failure logic, stage 1 835 Bfail2 Trip 3ph CB Fail PSL Input Protection Event Three phase output from circuit breaker failure logic, stage 2 835 CB1 Fail2 Trip CB Fail PSL Input Protection Event Three phase output from circuit breaker 1 failure logic, stage 2 836 CB2 Fail1 Trip CB Fail PSL Input Protection Event Three phase output from circuit breaker 2 failure logic, stage 1 837 CB2 Fail2 Trip CB Fail PSL Input Protection Event Three phase output from circuit breaker 2 failure logic, stage 2 892 Pole Dead A Poledead logic PSL Input Protection Event Phase A Pole Dead 893 Pole Dead B Poledead logic PSL Input Protection Event Phase B Pole Dead 894 Pole Dead C Poledead logic PSL Input Protection Event Phase C Pole Dead 1672 CB Fail1 Trip A CB Fail PSL Input Protection Event Phase A output from circuit breaker failure logic, stage 1 1673 CB Fail1 Trip B CB Fail PSL Input Protection Event Phase B output from circuit breaker failure logic, stage 1 1674 CB Fail1 Trip C CB Fail PSL Input Protection Event Phase C output from circuit breaker failure logic, stage 1 1675 CB Fail2 Trip A CB Fail PSL Input Protection Event Phase A output from circuit breaker failure logic, stage 2 1676 CB Fail2 Trip B CB Fail PSL Input Protection Event Phase B output from circuit breaker failure logic, stage 2 1677 CB Fail2 Trip C CB Fail PSL Input Protection Event Phase C output from circuit breaker failure logic, stage 2 1672 CB1 Fail1 Trip A CB Fail PSL Input Protection Event Phase A output from circuit breaker 1 failure logic, stage 1 1673 CB1 Fail1 Trip B CB Fail PSL Input Protection Event Phase B output from circuit breaker 1 failure logic, stage 1 1674 CB1 Fail1 Trip C CB Fail PSL Input Protection Event 16 P443-6/P543-7/P841-RNC1-TM-EN-1
P443-6/P543-7/P841 Supplement 1 - P443-6/P543-7/P841 Release Notes Ordinal English Text Source Type Response Function Description Phase C output from circuit breaker 1 failure logic, stage 1 1675 CB1 Fail2 Trip A CB Fail PSL Input Protection Event Phase A output from circuit breaker 1 failure logic, stage 2 1676 CB1 Fail2 Trip B CB Fail PSL Input Protection Event Phase B output from circuit breaker 1 failure logic, stage 2 1677 CB1 Fail2 Trip C CB Fail PSL Input Protection Event Phase C output from circuit breaker 1 failure logic, stage 2 1678 CB2 Fail1 Trip A CB Fail PSL Input Protection Event Phase A output from circuit breaker 2 failure logic, stage 1 1679 CB2 Fail1 Trip B CB Fail PSL Input Protection Event Phase B output from circuit breaker 2 failure logic, stage 1 1680 CB2 Fail1 Trip C CB Fail PSL Input Protection Event Phase C output from circuit breaker 2 failure logic, stage 1 1681 CB2 Fail2 Trip A CB Fail PSL Input Protection Event Phase A output from circuit breaker 2 failure logic, stage 2 1682 CB2 Fail2 Trip B CB Fail PSL Input Protection Event Phase B output from circuit breaker 2 failure logic, stage 2 1683 CB2 Fail2 Trip C CB Fail PSL Input Protection Event Phase C output from circuit breaker 2 failure logic, stage 2 P443-6/P543-7/P841-RNC1-TM-EN-1 17
Supplement 1 - P443-6/P543-7/P841 Release Notes P443-6/P543-7/P841 18 P443-6/P543-7/P841-RNC1-TM-EN-1
Alstom Grid - ALSTOM 2013. All rights reserved. Information contained in this document is indicative only. No representation or warranty is given or should be relied on that it is complete or correct or will apply to any particular project. This will depend on the technical and commercial circumstances. It is provided without liability and is subject to change without notice. Reproduction, use or disclosure to third parties, without express written authority, is strictly prohibited. Alstom Grid Worldwide Contact Centre www.alstom.com/grid/contactcentre/ Tel: +44 (0) 1785 250 070 www.alstom.com