FPGA Acceleration of Monte-Carlo Based Credit Derivatives Pricing

Transcription

1 FPGA Acceleraton of Monte-Carlo Based Credt Dervatves Prcng Alexander Kaganov 1, Asf Lakhany 2, Paul Chow 1 1 Department of Electrcal and Computer Engneerng, Unversty of Toronto 2 Quanttatve Research, Algorthmcs Incorporated

2 Increasng Computatonal Requrements (1/3) In recent years the fnancal ndustry has seen: 1. Increasng contract/model complexty Every year new models are developed Unavalablty of closed-form soluton Necesstate Monte-Carlo prcng

3 Increasng Computatonal Requrements (2/3) 2. Increasng portfolo szes Increase n smple nstruments Bonds Loans Increase n complex dervate securty CDO ssuance has ncreased from $157 bllon n 2004 to $507 bllon n 2007 (>3x)¹ N nstruments Y tme ¹ SIFMA 3xN nstruments 3xY tme (at least)

4 Increasng Computatonal Requrements (3/3) 3. Ever-present need to make real-tme decsons Market trends can change quckly Instruments traded electroncally 1 ms n Latency s Worth $100 M n Stock Tradng Busness Value (AMD Analyst Day-26 july 2007)

5 Trends n Fnancal Monte-Carlo Algorthms 1. Computatonally ntensve Converges n 1 N 2. Hghly repettve A large porton of the calculaton tme s spent n a small porton of the code (~90% of the tme s spent n ~10% of the code) 3. Hgh degree of coarse and fne-gran parallelsm Fne-Gran Coarse-Gran Typcal MC Fnancal smulaton

6 Collateralzed Debt Oblgaton (CDO)

7 CDO Problem: Banks typcally hold portfolos wth hghly volatle assets. Soluton: Sell assets to an outsde entty (SPV), whch combnes the dfferent assets together nto one collateral pool Repackage the pool as CDO tranches. Sell tranches as form of protecton to nvestors n return for premum payments

8 CDO Structure (1/2) Investors Borrowers Super Senor: 12%-100% Bonds Loans CDS CDOs Sponsor (Bank) (Credt Default Swap) Collateral Pool SPV Senor: 6% -12% Mezzanne: 3% -6% Equty: 0% -3% Tranches

9 CDO Structure (2/2) Each tranche has attachment and detachment ponts Losses below attachment pont the tranche s unaffected Losses above the detachment pont the tranche becomes nactve Investor premum s pad based on the tranche wdth mnus tranche losses Mezzanne Tranche: Detachment (6%) 4% Attachment (3%) Investor Premum Payments Tranche Losses Pad premum on the full nvestment Losses 1/3 of the prncpal nvestment. Pad based on 2/3 of the orgnal nvestment

10 Prcng a CDO Default Leg: expected losses of the tranche over the lfe of the contract Premum Leg: expected premums that the tranche nvestor wll receve over the lfe of the contract CDO Tranche Value = Premum Leg Default Leg T T E s ( S L ) d ) E ( L L 1 ) d ) 1 1 S =tranche thckness d = Dscount factor s = Premum L = Tranche loses at tme nterval

11 L s One-Factor Gaussan Copula (OFGC) Model Calculate total losses by averagng over all Monte-Carlo (MC) paths For each path: Systemc Factor Idosyncratc Factor 1. Generate: Y X 1 2 Z 2. Compare: 3. Record losses: Y 1 [ P ( t)]

12 Implementaton

13 Mult-Core Archtecture Three portons: Dstrbutor, OFGC prcng cores, and Collector. All cores have the same nput data except for market scenaros Coarse Gran Parallelsm: MC paths dvded among OFGC cores Data transfer occurs n parallel to calculatons Double Bufferng Maxmal requred data transfer rate of: 24MBytes/sec 1-Lane PCI express- 250 MBytes/sec Data transfer latency can be hdden

14 OFGC Desgn Phase 1: Generate Y Phase 2: Compare Y <Φ -1 [P(τ <t)]. Record partal losses Phase 3: Combne the partal sums, L(t ) s. Phase 4: Convert collateral pool losses to tranche losses Phase 5: Accumulate tranche losses

15 Phase 2 Compare Y <Φ -1 [P(τ <t)]. Record Losses Fne-gran parallelsm: parallelze over tme 8 replcas More replcas hgher speedup (potentally) However, large portons of the hardware become underutlzed Ppelned adder latency creates multple partal sums

16 OFGC Desgn Phase 1: Generate Y Phase 2: Compare Y <Φ -1 [P(τ <t)]. Record partal losses Phase 3: Combne the partal sums, L(t ) s. Phase 4: Convert collateral pool losses to tranche losses Phase 5: Accumulate tranche losses Phase 5: Accumulate tranche losses

17 Experments and Results Three notonal representatons were explored: floatng-pont sngle-precson, double-precson, and fxed-pont. Floatng-Pont DSP exploraton Sngle-Precson/Double-Precson Hybrd Fxed-Pont Performance Results

18 ¹ Dagram taken from Xlnx webste Floatng-Pont DSP Exploraton: DSP48E Background Hghly optmzed slces dedcated to arthmetc operatons Potental clock frequency 550 MHz Support for over 40 operatng modes: multpler multpleraccumulator three nput adder Vrtex 5 DSP48E Slce Dagram¹ barrel shfter wde bus multplexers etc

19 Floatng-Pont DSP Exploraton: Results Floatng-Pont Sngle- Precson Wthout DSP Wth DSP Flp-Flops (-8.0%) LUTs (-18.6%) BRAMs DSP48Es 9 29 (+222%) Frequency (+5.8%) Average Error (%) 0.39 [1.07] Floatng-Pont Double- Precson Wthout DSP Wth DSP Flp-Flops (-5.2%) LUTs (-1.6%) BRAMs DSP48Es (+300%) Frequency (+1.9%) Average Error (%) 0 Sngle-Precson s 1.5 to 2 tmes smaller but has an accuracy error

20 Sngle-Precson/Double-Precson Hybrd Combne the accuracy of the double-precson and resource utlzaton of sngle-precson Sngle-precson notonals and double-precson accumulator at phase 5 Sngle Precson Hybrd Flp-Flops (+2.9%) LUTs (+7.8%) BRAMs DSP48Es (+3.4%) Frequency (-1.6%) Average Error (%) 0.37 [1.07] 3.02E-5 [5.27E-5]

21 Fxed-Pont 42-bt notonals, 54-bt fnal accumulator matches the accuracy of a doubleprecson desgn Each addtonal notonal bt requres 62 Flp-Flops and 74 LUTs. Sngle Precson Fxed-Pont Flp-Flops (-24.9%) LUTs (-25.9%) BRAMs DSP48Es 29 7 (-75.9%) Frequency (+7.8%) Average Error (%) 0.37 [1.07] 0

22 Performance: Benchmarks # Based on Data From # of Assets # of Tme Steps # of Default Curves 1 CDX.NA.HY CDX.NA.IG CDX.NA.IG.HVOL CDX.NA.XO CDX.EM CDX.DIVERSIFIED CDX.NA.HY.BB CDX.NA.HY.B Credt ratng and number of nstruments are based on Dow Jones CDX Notonals obtaned from Moody s, range from $600,000 to $6.6 bllon α: unformly dstrbuted n [0, 1] Recovery rate: Normally dstrbuted, N (0.4,0.15) # of Tme Steps: Normally dstrbuted, N (20,10) 9 Sem-homogenous

23 Processor vs. FPGA setup 3.4 GHz Intel Xeon Processor 3GB RAM C++ program 100,000 Monte-Carlo paths Vrtex 5 SX50T speed grade -3 Connected to host through PCI express 100,000 Monte-Carlo paths

24 Speedup AVERAGE Sem-homogenous CDX.NA.HY.B CDX.NA.HY.BB CDX.DIVERSIFIED CDX.EM CDX.NA.XO CDX.NA.IG.HVOL CDX.NA.IG CDX.NA.HY Performance: Sngle Core Results (1/2) Double Precson Sngle Precson Sngle/Double Hybrd Fxed Pont 5 0 Benchmarks

25 Performance: Sngle Core Results (2/2) Sngle Core Average Acceleraton: Double Precson: 10.6 X Sngle Precson: 13.9 X Sngle/Double Hybrd: 13.6 X Fxed Pont: 15.6 X

26 Performance: Mult-Core Monte-Carlo paths ndependence allows for a lnear speedup as more prcng cores are ncorporated. Double Sngle Sngle/Double Hybrd Fxed - Pont Sngle Core Acceleraton Maxmum # of Instantatons Mult-Core Acceleraton 10.6X 13.9X 13.6X 15.6X X 46.5X 46.8X 63.5X

27 Summary Presented a hardware archtecture for prcng Collateralzed Debt Oblgatons usng L s model Demonstrated the advantages of usng DSP48Es n terms of resource utlzaton and frequency Especally evdent for sngle precson Establshed that ether a sngle/double hybrd or fxed-pont representatons could be used to balance resource utlzaton and accuracy Fxed-pont hardware desgn s over 63-fold faster than a correspondng software mplementaton

28 Future Work 1. Expand to Mult-Factor model m Y ( a X ) j 1 j j Z 2. Attempt the algorthm on a dfferent accelerator archtecture GPU

29 Thank You (Questons?)